Junjie Mao <junjie....@hotmail.com> writes:
> Manos Pitsidianakis <manos.pitsidiana...@linaro.org> writes:
>
>> This commit adds a re-implementation of hw/char/pl011.c in Rust.
>>
>> How to build:
>>
>> 1. Configure a QEMU build with:
>> --enable-system --target-list=aarch64-softmmu --enable-rust
>> 2. Launching a VM with qemu-system-aarch64 should use the Rust version
>> of the pl011 device
>>
>> Co-authored-by: Junjie Mao <junjie....@intel.com>
>> Co-authored-by: Paolo Bonzini <pbonz...@redhat.com>
>> Signed-off-by: Junjie Mao <junjie....@intel.com>
>> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
>> Signed-off-by: Manos Pitsidianakis <manos.pitsidiana...@linaro.org>
>> ---
> [snip]
>> diff --git a/rust/hw/char/pl011/src/device.rs
>> b/rust/hw/char/pl011/src/device.rs
>> new file mode 100644
>> index
>> 0000000000000000000000000000000000000000..6bd121b83ae831e838b05d83b67c698474b00b4a
>> --- /dev/null
>> +++ b/rust/hw/char/pl011/src/device.rs
>> @@ -0,0 +1,600 @@
>> +// Copyright 2024, Linaro Limited
>> +// Author(s): Manos Pitsidianakis <manos.pitsidiana...@linaro.org>
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +
>> +use core::{
>> + ffi::{c_int, c_uchar, c_uint, c_void, CStr},
>> + ptr::{addr_of, addr_of_mut, NonNull},
>> +};
>> +
>> +use qemu_api::{
>> + bindings::{self, *},
>> + definitions::ObjectImpl,
>> +};
>> +
>> +use crate::{
>> + memory_ops::PL011_OPS,
>> + registers::{self, Interrupt},
>> + RegisterOffset,
>> +};
>> +
>> +static PL011_ID_ARM: [c_uchar; 8] = [0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0,
>> 0x05, 0xb1];
>> +
>> +const DATA_BREAK: u32 = 1 << 10;
>> +
>> +/// QEMU sourced constant.
>> +pub const PL011_FIFO_DEPTH: usize = 16_usize;
>> +
>> +#[repr(C)]
>> +#[derive(Debug, qemu_api_macros::Object)]
>> +/// PL011 Device Model in QEMU
>> +pub struct PL011State {
>> + pub parent_obj: SysBusDevice,
>> + pub iomem: MemoryRegion,
>> + #[doc(alias = "fr")]
>> + pub flags: registers::Flags,
>> + #[doc(alias = "lcr")]
>> + pub line_control: registers::LineControl,
>> + #[doc(alias = "rsr")]
>> + pub receive_status_error_clear: registers::ReceiveStatusErrorClear,
>> + #[doc(alias = "cr")]
>> + pub control: registers::Control,
>> + pub dmacr: u32,
>> + pub int_enabled: u32,
>> + pub int_level: u32,
>> + pub read_fifo: [u32; PL011_FIFO_DEPTH],
>> + pub ilpr: u32,
>> + pub ibrd: u32,
>> + pub fbrd: u32,
>> + pub ifl: u32,
>
> Some of the fields can be private to the implementation of PL011State.
>
Forgot to mention, all those are minor comments that came to my mind
when I studied your code. Feel free to defer them to future
series. Thanks.
--
Best Regards
Junjie Mao
