From: Richard Henderson <richard.hender...@linaro.org>
AdvSIMD instructions are supposed to zero bits beyond 128.
Affects SSHLL, USHLL, SSHLL2, USHLL2.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20240717060903.205098-15-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
(cherry picked from commit 8e0c9a9efa21a16190cbac288e414bbf1d80f639)
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 922a16e5d4..7d620ef109 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -10263,6 +10263,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool
is_q, bool is_u,
tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
write_vec_element(s, tcg_rd, rd, i, size + 1);
}
+ clear_vec_high(s, true, rd);
}
/* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
--
2.39.2
