On Tue, Aug 20, 2024 at 2:11 AM Ian Brockbank <ian.brockb...@cirrus.com> wrote:
>
> From: Ian Brockbank <ian.brockb...@cirrus.com>
>
> The interrupt-level threshold (xintthresh) CSR holds an 8-bit field
> for the threshold level of the associated privilege mode.
>
> For horizontal interrupts, only the ones with higher interrupt levels
> than the threshold level are allowed to preempt.
>
> Signed-off-by: Ian Brockbank <ian.brockb...@cirrus.com>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_bits.h | 2 ++
> target/riscv/csr.c | 28 ++++++++++++++++++++++++++++
> 3 files changed, 32 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 95303f50d3..9b5f36ad0a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -260,6 +260,7 @@ struct CPUArchState {
>
> uint64_t miclaim;
> uint64_t mintstatus; /* clic-spec */
> + target_ulong mintthresh; /* clic-spec */
>
> uint64_t mie;
> uint64_t mideleg;
> @@ -283,6 +284,7 @@ struct CPUArchState {
> target_ulong stvec;
> target_ulong sepc;
> target_ulong scause;
> + target_ulong sintthresh; /* clic-spec */
>
> target_ulong mtvec;
> target_ulong mepc;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 2e65495b54..ad45402370 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -166,6 +166,7 @@
> #define CSR_MTVAL 0x343
> #define CSR_MIP 0x344
> #define CSR_MINTSTATUS 0xfb1 /* clic-spec-draft */
> +#define CSR_MINTTHRESH 0x347 /* clic-spec-draft */
>
> /* Machine-Level Window to Indirectly Accessed Registers (AIA) */
> #define CSR_MISELECT 0x350
> @@ -208,6 +209,7 @@
> #define CSR_STVAL 0x143
> #define CSR_SIP 0x144
> #define CSR_SINTSTATUS 0xdb1 /* clic-spec-draft */
> +#define CSR_SINTTHRESH 0x147 /* clic-spec-draft */
>
> /* Sstc supervisor CSRs */
> #define CSR_STIMECMP 0x14D
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index f9ed7b9079..9c824c0d8f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2903,6 +2903,18 @@ static int read_mintstatus(CPURISCVState *env, int
> csrno, target_ulong *val)
> return RISCV_EXCP_NONE;
> }
>
> +static int read_mintthresh(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->mintthresh;
> + return 0;
> +}
> +
> +static int write_mintthresh(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + env->mintthresh = val;
We should be clearing the upper bits on a write
Alistair
> + return 0;
> +}
> +
> /* Supervisor Trap Setup */
> static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
> Int128 *val)
> @@ -3322,6 +3334,18 @@ static int read_sintstatus(CPURISCVState *env, int
> csrno, target_ulong *val)
> return RISCV_EXCP_NONE;
> }
>
> +static int read_sintthresh(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->sintthresh;
> + return 0;
> +}
> +
> +static int write_sintthresh(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + env->sintthresh = val;
> + return 0;
> +}
> +
> /* Supervisor Protection and Translation */
> static RISCVException read_satp(CPURISCVState *env, int csrno,
> target_ulong *val)
> @@ -5621,9 +5645,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> /* Machine Mode Core Level Interrupt Controller */
> [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus },
> + [CSR_MINTTHRESH] = { "mintthresh", clic, read_mintthresh,
> + write_mintthresh },
>
> /* Supervisor Mode Core Level Interrupt Controller */
> [CSR_SINTSTATUS] = { "sintstatus", clic, read_sintstatus },
> + [CSR_SINTTHRESH] = { "sintthresh", clic, read_sintthresh,
> + write_sintthresh },
>
> [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf,
> .min_priv_ver = PRIV_VERSION_1_12_0 },
> --
> 2.46.0.windows.1
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