Re: [PATCH 1/1] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension

[Daniel Henrique Barboza]

On 9/2/24 7:34 AM, Maria Klauchek wrote:

FCSR is a part of F extension. Print it to log if FPU option is enabled.

Signed-off-by: Maria Klauchek <m.klauc...@syntacore.com>
---

Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

  target/riscv/cpu.c | 6 ++++++
  1 file changed, 6 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a90808a3ba..6ff6096777 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -839,6 +839,12 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, 
int flags)
          }
      }
      if (flags & CPU_DUMP_FPU) {
+        target_ulong val = 0;
+        RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0);
+        if (res == RISCV_EXCP_NONE) {
+            qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+                    csr_ops[CSR_FCSR].name, val);
+        }
          for (i = 0; i < 32; i++) {
              qemu_fprintf(f, " %-8s %016" PRIx64,
                           riscv_fpr_regnames[i], env->fpr[i]);