On 8/30/24 19:06, Mike Kowal wrote:
On 8/30/2024 3:25 AM, Cédric Le Goater wrote:
On 8/29/24 22:35, Mike Kowal wrote:
On 8/29/2024 7:29 AM, Cédric Le Goater wrote:
On 8/1/24 22:30, Michael Kowal wrote:
From: Glenn Miles <mil...@linux.vnet.ibm.com>
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Did you confirm with the HW designer ?
AFAIR, the PIPR is constructed from the IPB and the later is it updated
the better. However, if now, both PIPR (HW and Pool) are required to
identify the ctx to notify, I agree set_cppr() needs a change but what
about xive_tctx_ipb_update() which is called when an interrupt
needs a resend ?
This was fix to a bug and matches what is specified in the XIVE2 architecture
document CPPR flows (MMIO CPPR xxx processing).
ok. I was also wondering if this was fixing a bug. Do you think this
is the correct commit id ?
cdd4de68edb6 ("ppc/xive: notify the CPU when the interrupt priority is more
privileged")
If so, could you please add a Fixes tags ?
Thanks,
C.
Many of these parts have been changed multiple time for different things. I am not sure which commit this fixes.
I use 'tig blame <file>' to dig change history.
I am upstreaming other peoples work that was done over the last couple of
years so it hard to tell. Also, the original xive support was only complete
enough to support Linux. Much of this I would consider 'new development'
expanding XIVE support for Power VM. If you think it should still have a
fixes-tag, I will add it.
I think this is the right commit, please add it.
Could you also add your self as a Reviewer ?
Thanks,
C.
