On Tue, Aug 27, 2024 at 1:32 AM Deepak Gupta <de...@rivosinc.com> wrote:
>
> sw check exception support was recently added. This patch further augments
> sw check exception by providing support for additional code which is
> provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever
> sw check exception is raised *tval gets the value deposited in
> `sw_check_code`.
>
> Signed-off-by: Deepak Gupta <de...@rivosinc.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h        | 2 ++
>  target/riscv/cpu_helper.c | 3 +++
>  target/riscv/csr.c        | 1 +
>  3 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7be0fa30f7..11c6513a90 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -224,6 +224,8 @@ struct CPUArchState {
>
>      /* elp state for zicfilp extension */
>      bool      elp;
> +    /* sw check code for sw check exception */
> +    target_ulong sw_check_code;
>  #ifdef CONFIG_USER_ONLY
>      uint32_t elf_flags;
>      bool ufcfien;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 12484ca7d2..121fef1be6 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1761,6 +1761,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>                  cs->watchpoint_hit = NULL;
>              }
>              break;
> +        case RISCV_EXCP_SW_CHECK:
> +            tval = env->sw_check_code;
> +            break;
>          default:
>              break;
>          }
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5771a14848..a5a969a377 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1179,6 +1179,7 @@ static const uint64_t all_ints = M_MODE_INTERRUPTS | 
> S_MODE_INTERRUPTS |
>                           (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
>                           (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
>                           (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
> +                         (1ULL << (RISCV_EXCP_SW_CHECK)) | \
>                           (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
>                           (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
>                           (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
> --
> 2.44.0
>
>

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