On 8/24/24 14:56, Ajeet Singh wrote:
From: Mark Corbin<m...@dibsco.co.uk>
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin<m...@dibsco.co.uk>
Signed-off-by: Ajeet Singh<itac...@freebsd.org>
Co-authored-by: Jessica Clarke<jrt...@jrtc27.com>
---
bsd-user/riscv/target_arch_cpu.h | 39 ++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_cpu.h
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
