Re: [PATCH v8 04/17] target/riscv: additional code information for sw check

[Richard Henderson]

On 8/24/24 05:01, Deepak Gupta wrote:

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 12484ca7d2..9f08a67a9e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1761,6 +1761,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
                  cs->watchpoint_hit = NULL;
              }
              break;
+        case RISCV_EXCP_SW_CHECK:
+            tval = env->sw_check_code;
          default:

Missing break.
This should have warned about fall through...



r~