On 8/22/24 07:50, Deepak Gupta wrote:
zicfiss protects shadow stack using new page table encodings PTE.W=0,
PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not
implemented or if shadow stack are not enabled.
Loads on shadow stack memory are allowed while stores to shadow stack
memory leads to access faults. Shadow stack accesses to RO memory
leads to store page fault.
To implement special nature of shadow stack memory where only selected
stores (shadow stack stores from sspush) have to be allowed while rest
of regular stores disallowed, new MMU TLB index is created for shadow
stack.
Signed-off-by: Deepak Gupta<de...@rivosinc.com>
Suggested-by: Richard Henderson<richard.hender...@linaro.org>
---
target/riscv/cpu_helper.c | 37 +++++++++++++++++++++++++++++++------
target/riscv/internals.h | 3 +++
2 files changed, 34 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
