On 8/22/24 07:50, Deepak Gupta wrote:
zicfiss introduces a new state ssp ("shadow stack register") in cpu. ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds virtual address for shadow stack as programmed by software.Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs. Shadow stack can be enabled for a mode only if it's higher privileged mode had it enabled for itself. M mode doesn't need enabling control, it's always available if extension is available on cpu. This patch also implements helper bcfi function which determines if bcfi is enabled at current privilege or not. qemu-user also gets field `ubcfien` indicating whether qemu user has shadow stack enabled or not. Adds ssp to migration state as well. Signed-off-by: Deepak Gupta<de...@rivosinc.com> Co-developed-by: Jim Shu<jim....@sifive.com> Co-developed-by: Andy Chiu<andy.c...@sifive.com> --- target/riscv/cpu.c | 5 ++++ target/riscv/cpu.h | 4 +++ target/riscv/cpu_bits.h | 6 +++++ target/riscv/cpu_helper.c | 25 +++++++++++++++++++ target/riscv/csr.c | 52 +++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 19 ++++++++++++++ 6 files changed, 111 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
