On Thu, Aug 01, 2024 at 12:43:25PM GMT, Daniel Henrique Barboza wrote: > The RISC-V IOMMU PCI device we're going to add next is a reference > implementation of the riscv-iommu spec [1], which predicts that the > IOMMU can be implemented as a PCIe device. > > However, RISC-V International (RVI), the entity that ratified the > riscv-iommu spec, didn't bother assigning a PCI ID for this IOMMU PCIe > implementation that the spec predicts. This puts us in an uncommon > situation because we want to add the reference IOMMU PCIe implementation > but we don't have a PCI ID for it. > > Given that RVI doesn't provide a PCI ID for it we reached out to Red Hat > and Gerd Hoffman, and they were kind enough to give us a PCI ID for the > RISC-V IOMMU PCI reference device. > > Thanks Red Hat and Gerd for this RISC-V IOMMU PCIe device ID. > > [1] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0 > > Cc: Gerd Hoffmann <kra...@redhat.com> > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > Reviewed-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Gerd Hoffmann <kra...@redhat.com>
