On 8/20/24 10:01, Deepak Gupta wrote:
Implements setting lp expected when `jalr` is encountered and implements
`lpad` instruction of zicfilp. `lpad` instruction is taken out of
auipc x0, <imm_20>. This is an existing HINTNOP space. If `lpad` is
target of an indirect branch, cpu checks for 20 bit value in x7 upper
with 20 bit value embedded in `lpad`. If they don't match, cpu raises a
sw check exception with tval = 2.
Signed-off-by: Deepak Gupta <de...@rivosinc.com>
Co-developed-by: Jim Shu <jim....@sifive.com>
Co-developed-by: Andy Chiu <andy.c...@sifive.com>
---
target/riscv/cpu_user.h | 1 +
target/riscv/insn32.decode | 5 ++-
target/riscv/insn_trans/trans_rvi.c.inc | 55 +++++++++++++++++++++++++
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h
index 02afad608b..e6927ff847 100644
--- a/target/riscv/cpu_user.h
+++ b/target/riscv/cpu_user.h
@@ -15,5 +15,6 @@
#define xA6 16
#define xA7 17 /* syscall number for RVI ABI */
#define xT0 5 /* syscall number for RVE ABI */
+#define xT2 7
#endif
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c45b8fa1d8..6533cb0758 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -123,7 +123,10 @@ sfence_vm 0001000 00100 ..... 000 00000 1110011
@sfence_vm
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
-auipc .................... ..... 0010111 @u
+{
+ lpad label:20 00000 0010111
+ auipc .................... ..... 0010111 @u
+}
jal .................... ..... 1101111 @j
Again, best to line up the decode bits.
While you are required to add two spaces within { },
you can remove two spaces before the first '.':
lui .................... ..... 0110111 @u
{
lpad label:20 00000 0010111
auipc .................... ..... 0010111 @u
}
jal .................... ..... 1101111 @j
Otherwise,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
