On Thu, 8 Aug 2024 14:26:35 +0200
Mauro Carvalho Chehab <mchehab+hua...@kernel.org> wrote:
> Accurately injecting an ARM Processor error ACPI/APEI GHES
> error record requires the value of the ARM Multiprocessor
> Affinity Register (mpidr).
>
> While ARM implements it, this is currently not visible.
>
> Add a field at CPU storing it, and place it at arm_cpu_properties
> as experimental, thus allowing it to be queried via QMP using
> qom-get function.
looks fine to me, but it's upto ARM folk to ack this
> Signed-off-by: Mauro Carvalho Chehab <mchehab+hua...@kernel.org>
> ---
> target/arm/cpu.c | 1 +
> target/arm/cpu.h | 1 +
> target/arm/helper.c | 10 ++++++++--
> 3 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 19191c239181..30fcf0a10f46 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2619,6 +2619,7 @@ static ObjectClass *arm_cpu_class_by_name(const char
> *cpu_model)
>
> static Property arm_cpu_properties[] = {
> DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
> + DEFINE_PROP_UINT64("x-mpidr", ARMCPU, mpidr, 0),
> DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
> mp_affinity, ARM64_AFFINITY_INVALID),
> DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index a12859fc5335..d2e86f0877cc 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1033,6 +1033,7 @@ struct ArchCPU {
> uint64_t reset_pmcr_el0;
> } isar;
> uint64_t midr;
> + uint64_t mpidr;
> uint32_t revidr;
> uint32_t reset_fpsid;
> uint64_t ctr;
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 8fb4b474e83f..16e75b7c5ed9 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4692,7 +4692,7 @@ static uint64_t mpidr_read_val(CPUARMState *env)
> return mpidr;
> }
>
> -static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +static uint64_t mpidr_read(CPUARMState *env)
> {
> unsigned int cur_el = arm_current_el(env);
>
> @@ -4702,6 +4702,11 @@ static uint64_t mpidr_read(CPUARMState *env, const
> ARMCPRegInfo *ri)
> return mpidr_read_val(env);
> }
>
> +static uint64_t mpidr_read_ri(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> + return mpidr_read(env);
> +}
> +
> static const ARMCPRegInfo lpae_cp_reginfo[] = {
> /* NOP AMAIR0/1 */
> { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
> @@ -9723,7 +9728,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
> .fgt = FGT_MPIDR_EL1,
> - .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
> + .access = PL1_R, .readfn = mpidr_read_ri, .type =
> ARM_CP_NO_RAW },
> };
> #ifdef CONFIG_USER_ONLY
> static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = {
> @@ -9733,6 +9738,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo);
> #endif
> define_arm_cp_regs(cpu, mpidr_cp_reginfo);
> + cpu->mpidr = mpidr_read(env);
> }
>
> if (arm_feature(env, ARM_FEATURE_AUXCR)) {
