On Thu, Jun 8, 2023 at 5:52 PM Andrew Jones <ajo...@ventanamicro.com> wrote:
>
>
> Please add a commit message to all patches of the series.
>
> Another comment below.
Thanks for the suggestion, I'll add commit messages to all patches in
the v5 patches.
>
> On Thu, Jun 08, 2023 at 12:23:11AM -0700, Tommy Wu wrote:
> > Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> > Signed-off-by: Tommy Wu <tommy...@sifive.com>
> > ---
> > hw/riscv/riscv_hart.c | 21 +++++++++++++++++++++
> > include/hw/riscv/riscv_hart.h | 4 ++++
> > target/riscv/cpu.c | 13 +++++++++++++
> > target/riscv/cpu.h | 7 +++++++
> > target/riscv/cpu_bits.h | 12 ++++++++++++
> > target/riscv/cpu_helper.c | 24 ++++++++++++++++++++++++
> > 6 files changed, 81 insertions(+)
> >
> > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> > index 613ea2aaa0..eac18f8c29 100644
> > --- a/hw/riscv/riscv_hart.c
> > +++ b/hw/riscv/riscv_hart.c
> > @@ -33,6 +33,12 @@ static Property riscv_harts_props[] = {
> > DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
> > DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
> > DEFAULT_RSTVEC),
> > + DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState,
> > + num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64,
> > + uint64_t),
> > + DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState,
> > + num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64,
> > + uint64_t),
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > @@ -47,6 +53,21 @@ static bool riscv_hart_realize(RISCVHartArrayState *s,
> > int idx,
> > {
> > object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
> > cpu_type);
> > qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
> > +
> > + if (s->harts[idx].cfg.ext_smrnmi) {
> > + if (s->rnmi_irqvec) {
> > + qdev_prop_set_uint64(DEVICE(&s->harts[idx]),
> > + "rnmi-interrupt-vector",
> > + s->rnmi_irqvec[idx]);
> > + }
> > +
> > + if (s->rnmi_excpvec) {
> > + qdev_prop_set_uint64(DEVICE(&s->harts[idx]),
> > + "rnmi-exception-vector",
> > + s->rnmi_excpvec[idx]);
> > + }
> > + }
> > +
> > s->harts[idx].env.mhartid = s->hartid_base + idx;
> > qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
> > return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
> > diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
> > index bbc21cdc9a..99c0ac5009 100644
> > --- a/include/hw/riscv/riscv_hart.h
> > +++ b/include/hw/riscv/riscv_hart.h
> > @@ -38,6 +38,10 @@ struct RISCVHartArrayState {
> > uint32_t hartid_base;
> > char *cpu_type;
> > uint64_t resetvec;
> > + uint32_t num_rnmi_irqvec;
> > + uint64_t *rnmi_irqvec;
> > + uint32_t num_rnmi_excpvec;
> > + uint64_t *rnmi_excpvec;
> > RISCVCPU *harts;
> > };
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index db0875fb43..c8dc0eaa87 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -119,6 +119,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
> > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> > + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
> > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
> > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
> > ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
> > @@ -1404,6 +1405,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq,
> > int level)
> > g_assert_not_reached();
> > }
> > }
> > +
> > +static void riscv_cpu_set_nmi(void *opaque, int irq, int level)
> > +{
> > + riscv_cpu_set_rnmi(RISCV_CPU(opaque), irq, level);
> > +}
> > #endif /* CONFIG_USER_ONLY */
> >
> > static void riscv_cpu_init(Object *obj)
> > @@ -1420,6 +1426,8 @@ static void riscv_cpu_init(Object *obj)
> > #ifndef CONFIG_USER_ONLY
> > qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
> > IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
> > + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi,
> > + "riscv.cpu.rnmi", RNMI_MAX);
> > #endif /* CONFIG_USER_ONLY */
> > }
> >
> > @@ -1600,6 +1608,7 @@ static Property riscv_cpu_extensions[] = {
> > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> > DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
> > DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
> > + DEFINE_PROP_BOOL("x-smrnmi", RISCVCPU, cfg.ext_smrnmi, false),
> >
> > DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
> > DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
> > @@ -1644,6 +1653,10 @@ static Property riscv_cpu_properties[] = {
> >
> > DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
> > DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
> > + DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irqvec,
> > + DEFAULT_RNMI_IRQVEC),
> > + DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec,
> > + DEFAULT_RNMI_EXCPVEC),
>
> Why are these addresses user configurable? Shouldn't each board set them
> to whatever the real board uses and a generic board, like 'virt', set
> them to whatever works for it, considering the rest of its memory map?
> Also, looking ahead, I don't see where the addresses are described to the
> M-mode software in the DT, which implies board-specific M-mode software
> would hard code it, but generic M-mode software should get the addresses
> from the DT. And, presumably, M-mode software should protect and reserve
> these addresses from S-mode. It'd be nice to see an M-mode software PoC,
> but I didn't see anything on the opensbi mailing list.
>
> Thanks,
> drew
Because the RNMI interrupt trap handler address isn't software configurable,
it’s implementation-defined. Although the generic M-mode software get the
addresses from the DT, the generic M-mode software cannot configure it like
`mtvec`. I think making it configurable in the QEMU helps users to test the
functionality of their own RNMI trap handler.
