From: TANG Tiancheng <tangtiancheng....@alibaba-inc.com>
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.
The recent commit 9b91879b51 ("hw/riscv/virt.c: Make block devices default to
virtio")
changed the default behavior of block devices in RISCV Virt. To maintain
compatibility
with the new behavior, add the "if=none" parameter to the "-drive" option in the
Avocado test suite.
Changed from:
'-drive', f'file={rootfs_path},format=raw,id=hd0'
to:
'-drive', f'file={rootfs_path},format=raw,id=hd0,if=none'
Test rawesult below:
$ make check-avocado
AVOCADO_TESTS=/home/developer/qemu/qemu-code-test/qemu/tests/avocado/boot_linux_console.py
...
AVOCADO tests/avocado
Fetching asset from
/home/developer/qemu/qemu-code-test/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
Fetching asset from
/home/developer/qemu/qemu-code-test/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i
JOB ID : fcacf90ad453010550f60d26166911aee2e2a514
JOB LOG :
/home/developer/qemu/qemu-code-test/qemu/build/tests/results/job-2024-07-08T12.30-fcacf90/job.log
(1/1)
/home/developer/qemu/qemu-code-test/qemu/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_riscv64_virt_rv32i:
PASS (27.64 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
JOB TIME : 28.39 s
v4:
Drop UL completely in PATCH v3 2/7, 4/7, 5/7.
Avocado: Add "if=none" to "-drive" option in QEMU command line
v3:
Rebase to the master branch
v2:
Remove the line that was inadvertently left in PATCH v1 4/6.
Add an avocado test.
v1:
https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
TANG Tiancheng (7):
target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
target/riscv: Correct SXL return value for RV32 in RV64 QEMU
target/riscv: Detect sxl to set bit width for RV32 in RV64
target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
target/riscv: Enable RV32 CPU support in RV64 QEMU
tests/avocado: Add an avocado test for riscv64
configs/targets/riscv64-softmmu.mak | 2 +-
hw/riscv/boot.c | 35 +++++++++++++++++----------
hw/riscv/sifive_u.c | 3 ++-
include/hw/riscv/boot.h | 4 +++-
include/hw/riscv/boot_opensbi.h | 29 ++++++++++++++++++++++
target/riscv/cpu.c | 17 +++++++++----
target/riscv/cpu.h | 5 +++-
target/riscv/cpu_helper.c | 25 +++++++++++++------
target/riscv/pmp.c | 2 +-
tests/avocado/boot_linux_console.py | 37 +++++++++++++++++++++++++++++
10 files changed, 131 insertions(+), 28 deletions(-)
--
2.43.0
