Add MIPS DSP Multiply instructions Support.
Signed-off-by: Jia Liu <pro...@gmail.com>
---
target-mips/dsp_helper.c | 729 ++++++++++++++++++++++++++++++++++++++++++++++
target-mips/helper.h | 34 +++
target-mips/translate.c | 264 +++++++++++++++++
3 files changed, 1027 insertions(+), 0 deletions(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 86f7df1..893e915 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -2250,6 +2250,735 @@ uint32_t helper_shrav_r_w(uint32_t rs, uint32_t rt)
return rd;
}
+/** DSP Multiply Sub-class insns **/
+uint32_t helper_muleu_s_ph_qbl(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3, rs2;
+ uint16_t tempB, tempA, rth, rtl;
+ uint32_t temp;
+ uint32_t rd;
+
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_mul_u8_u16(env, rs3, rth);
+ tempA = mipsdsp_mul_u8_u16(env, rs2, rtl);
+ temp = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+ rd = temp;
+ return rd;
+}
+
+uint32_t helper_muleu_s_ph_qbr(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs1, rs0;
+ uint16_t tempB, tempA;
+ uint16_t rth, rtl;
+ uint32_t temp;
+ uint32_t rd;
+
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs0 = rs & MIPSDSP_Q0;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_mul_u8_u16(env, rs1, rth);
+ tempA = mipsdsp_mul_u8_u16(env, rs0, rtl);
+ temp = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+ rd = temp;
+ return rd;
+}
+
+uint32_t helper_mulq_rs_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ int16_t tempB, tempA, rsh, rsl, rth, rtl;
+ int32_t temp;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_rndq15_mul_q15_q15(env, rsh, rth);
+ tempA = mipsdsp_rndq15_mul_q15_q15(env, rsl, rtl);
+ temp = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+ rd = temp;
+
+ return rd;
+}
+
+uint32_t helper_muleq_s_w_phl(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rth;
+ int32_t temp;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ temp = mipsdsp_mul_q15_q15_overflowflag21(env, rsh, rth);
+ rd = temp;
+
+ return rd;
+}
+
+uint32_t helper_muleq_s_w_phr(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ int16_t rsl, rtl;
+ int32_t temp;
+ uint32_t rd;
+
+ rsl = rs & MIPSDSP_LO;
+ rtl = rt & MIPSDSP_LO;
+ temp = mipsdsp_mul_q15_q15_overflowflag21(env, rsl, rtl);
+ rd = temp;
+
+ return rd;
+}
+
+void helper_dpau_h_qbl(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3, rs2;
+ uint8_t rt3, rt2;
+ uint16_t tempB, tempA;
+ uint64_t tempC, tempBL, tempAL, dotp;
+
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ tempB = mipsdsp_mul_u8_u8(rs3, rt3);
+ tempA = mipsdsp_mul_u8_u8(rs2, rt2);
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) + dotp;
+
+ env->active_tc.HI[ac] = (tempC & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempC & MIPSDSP_LLO;
+}
+
+void helper_dpau_h_qbr(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs1, rs0;
+ uint8_t rt1, rt0;
+ uint16_t tempB, tempA;
+ uint64_t tempC, tempBL, tempAL, dotp;
+
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rs0 = (rs & MIPSDSP_Q0);
+ rt0 = (rt & MIPSDSP_Q0);
+ tempB = mipsdsp_mul_u8_u8(rs1, rt1);
+ tempA = mipsdsp_mul_u8_u8(rs0, rt0);
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) + dotp;
+
+ env->active_tc.HI[ac] = (tempC & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempC & MIPSDSP_LLO;
+}
+
+void helper_dpsu_h_qbl(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3, rs2, rt3, rt2;
+ uint16_t tempB, tempA;
+ uint64_t dotp, tempBL, tempAL, tempC;
+
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+
+ tempB = mipsdsp_mul_u8_u8(rs3, rt3);
+ tempA = mipsdsp_mul_u8_u8(rs2, rt2);
+ tempBL = tempB & 0xFFFF;
+ tempAL = tempA & 0xFFFF;
+
+ dotp = tempBL + tempAL;
+ tempC = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ tempC -= dotp;
+
+ env->active_tc.HI[ac] = (tempC & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempC & MIPSDSP_LLO;
+}
+
+void helper_dpsu_h_qbr(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs1, rs0, rt1, rt0;
+ uint16_t tempB, tempA;
+ uint64_t dotp, tempBL, tempAL, tempC;
+
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs0 = (rs & MIPSDSP_Q0);
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = (rt & MIPSDSP_Q0);
+
+ tempB = mipsdsp_mul_u8_u8(rs1, rt1);
+ tempA = mipsdsp_mul_u8_u8(rs0, rt0);
+ tempBL = tempB & 0xFFFF;
+ tempAL = tempA & 0xFFFF;
+
+ dotp = tempBL + tempAL;
+ tempC = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ tempC -= dotp;
+
+ env->active_tc.HI[ac] = (tempC & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempC & MIPSDSP_LLO;
+}
+
+void helper_dpa_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl;
+ int32_t tempA, tempB;
+ int64_t acc, tempAL, tempBL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = (int32_t)rsh * (int32_t)rth;
+ tempA = (int32_t)rsl * (int32_t)rtl;
+ tempBL = tempB;
+ tempAL = tempA;
+
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ acc += tempBL + tempAL;
+
+ env->active_tc.HI[ac] = (acc & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = acc & MIPSDSP_LLO;
+}
+
+void helper_dpax_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t acc, dotp, tempBL, tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = (uint32_t)rsh * (uint32_t)rth;
+ tempA = (uint32_t)rsl * (uint32_t)rtl;
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ acc += dotp;
+
+ env->active_tc.HI[ac] = (acc & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = acc & MIPSDSP_LLO;
+}
+
+void helper_dpaq_s_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t acc, dotp, tempBL, tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_mul_q15_q15(env, ac, rsh, rth);
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rtl);
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ acc += dotp;
+
+ env->active_tc.HI[ac] = (acc & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = acc & MIPSDSP_LLO;
+}
+
+void helper_dpaqx_s_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t acc, dotp, tempBL, tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_mul_q15_q15(env, ac, rsh, rtl);
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rth);
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ acc += dotp;
+
+ env->active_tc.HI[ac] = (acc & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = acc & MIPSDSP_LLO;
+}
+
+void helper_dpaqx_sa_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA, tempC62_31, tempC63;
+ int64_t acc, dotp, tempBL, tempAL, tempC;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_mul_q15_q15(env, ac, rsh, rtl);
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rth);
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ tempC = acc + dotp;
+ tempC63 = (tempC >> 63) & 0x01;
+ tempC62_31 = (tempC >> 31) & 0xFFFFFFFF;
+
+ if ((tempC63 == 0) && (tempC62_31 == 0xFFFFFFFF)) {
+ tempC = 0x80000000;
+ set_DSPControl_overflow_flag(env, 1, 16 + ac);
+ }
+
+ env->active_tc.HI[ac] = (tempC & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempC & MIPSDSP_LLO;
+}
+
+void helper_dps_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t acc, dotp, tempBL, tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = (int32_t)rsh * (int32_t)rth;
+ tempA = (int32_t)rsl * (int32_t)rtl;
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ acc -= dotp;
+
+ env->active_tc.HI[ac] = (acc & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = acc & MIPSDSP_LLO;
+}
+
+void helper_dpsx_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t acc, dotp, tempBL, tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = (int32_t)rsh * (int32_t)rtl;
+ tempA = (int32_t)rsl * (int32_t)rth;
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ acc -= dotp;
+ env->active_tc.HI[ac] = (acc & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = acc & MIPSDSP_LLO;
+}
+
+void helper_dpsq_s_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t acc, dotp, tempBL, tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_mul_q15_q15(env, ac, rsh, rth);
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rtl);
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ acc -= dotp;
+
+ env->active_tc.HI[ac] = (acc & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = acc & MIPSDSP_LLO;
+}
+
+void helper_dpsqx_s_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t dotp, tempC, tempBL, tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_mul_q15_q15(env, ac, rsh, rtl);
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rth);
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) - dotp;
+
+ env->active_tc.HI[ac] = (tempC & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempC & MIPSDSP_LLO;
+}
+
+void helper_dpsqx_sa_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA, tempC63, tempC62_31;
+ int64_t dotp, tempBL, tempAL, tempC;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_mul_q15_q15(env, ac, rsh, rtl);
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rth);
+
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL + tempAL;
+ tempC = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ tempC -= dotp;
+
+ tempC63 = (tempC >> 63) & 0x01;
+ tempC62_31 = (tempC >> 31) & 0xFFFFFFFF;
+
+ if ((tempC63 == 0) && (tempC62_31 != 0)) {
+ tempC = 0x7FFFFFFF;
+ set_DSPControl_overflow_flag(env, 1, 16 + ac);
+ }
+
+ if ((tempC63 == 1) && (tempC62_31 != 0xFFFFFFFF)) {
+ tempC = 0xFFFFFFFF80000000ull;
+ set_DSPControl_overflow_flag(env, 1, 16 + ac);
+ }
+
+ env->active_tc.HI[ac] = (tempC & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempC & MIPSDSP_LLO;
+}
+
+void helper_mulsaq_s_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t tempBL, tempAL, acc, dotp;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_mul_q15_q15(env, ac, rsh, rth);
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rtl);
+ tempBL = tempB;
+ tempAL = tempA;
+ dotp = tempBL - tempAL;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ dotp = dotp + acc;
+ env->active_tc.HI[ac] = (dotp & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = dotp & MIPSDSP_LLO;
+}
+
+void helper_dpaq_sa_l_w(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int32_t temp64, temp63, tempacc63, tempdotp63, tempDL63;
+ int64_t dotp, acc;
+ int64_t tempDL[2];
+ uint64_t temp;
+
+ dotp = mipsdsp_mul_q31_q31(env, ac, rs, rt);
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ tempDL[0] = acc + dotp;
+
+ tempacc63 = (acc >> 63) & 0x01;
+ tempdotp63 = (dotp >> 63) & 0x01;
+ tempDL63 = (tempDL[0] >> 63) & 0x01;
+
+ if (((tempacc63 == 1) && (tempdotp63 == 1)) | \
+ (((tempacc63 == 1) || (tempdotp63 == 1)) && tempDL63 == 0)) {
+ tempDL[1] = 1;
+ } else {
+ tempDL[1] = 0;
+ }
+
+ temp = tempDL[0];
+ temp64 = tempDL[1] & 0x01;
+ temp63 = (tempDL[0] >> 63) & 0x01;
+
+ if (temp64 != temp63) {
+ if (temp64 == 1) {
+ temp = 0x8000000000000000ull;
+ } else {
+ temp = 0x7FFFFFFFFFFFFFFFull;
+ }
+
+ set_DSPControl_overflow_flag(env, 1, 16 + ac);
+ }
+
+ env->active_tc.HI[ac] = (temp & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = temp & MIPSDSP_LLO;
+}
+
+void helper_dpsq_sa_l_w(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int32_t temp64, temp63, tempacc63, tempdotp63, tempDL63;
+ int64_t dotp, acc;
+ int64_t tempDL[2];
+ uint64_t temp;
+
+ dotp = mipsdsp_mul_q31_q31(env, ac, rs, rt);
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ tempDL[0] = acc - dotp;
+
+ tempacc63 = (acc >> 63) & 0x01;
+ tempdotp63 = (dotp >> 63) & 0x01;
+ tempDL63 = (tempDL[0] >> 63) & 0x01;
+
+ if (((tempacc63 == 1) && (tempdotp63 == 0)) | \
+ (((tempacc63 == 1) || (tempdotp63 == 0)) && tempDL63 == 0)) {
+ tempDL[1] = 1;
+ } else {
+ tempDL[1] = 0;
+ }
+
+ temp = tempDL[0];
+ temp64 = tempDL[1] & 0x01;
+ temp63 = (tempDL[0] >> 63) & 0x01;
+ if (temp64 != temp63) {
+ if (temp64 == 1) {
+ temp = 0x8000000000000000ull;
+ } else {
+ temp = 0x7FFFFFFFFFFFFFFFull;
+ }
+ set_DSPControl_overflow_flag(env, 1, ac + 16);
+ }
+
+ env->active_tc.HI[ac] = (temp & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = temp & MIPSDSP_LLO;
+}
+
+void helper_maq_s_w_phl(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rth;
+ int32_t tempA;
+ int64_t tempL, tempAL, acc;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsh, rth);
+ tempAL = tempA;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ tempL = tempAL + acc;
+ env->active_tc.HI[ac] = (tempL & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempL & MIPSDSP_LLO;
+}
+
+void helper_maq_s_w_phr(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsl, rtl;
+ int32_t tempA;
+ int64_t tempL, tempAL, acc;
+
+ rsl = rs & MIPSDSP_LO;
+ rtl = rt & MIPSDSP_LO;
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rtl);
+ tempAL = tempA;
+ acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
+ ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ tempL = tempAL + acc;
+
+ env->active_tc.HI[ac] = (tempL & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempL & MIPSDSP_LLO;
+}
+
+void helper_maq_sa_w_phl(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rth;
+ int32_t tempA;
+ int64_t tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsh, rth);
+ tempA = mipsdsp_sat32_acc_q31(env, ac, tempA);
+ tempAL = tempA;
+
+ env->active_tc.HI[ac] = (tempAL & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempAL & MIPSDSP_LLO;
+}
+
+void helper_maq_sa_w_phr(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ int16_t rsl, rtl;
+ int32_t tempA;
+ int64_t tempAL;
+
+ rsl = rs & MIPSDSP_LO;
+ rtl = rs & MIPSDSP_LO;
+
+ tempA = mipsdsp_mul_q15_q15(env, ac, rsl, rtl);
+ tempA = mipsdsp_sat32_acc_q31(env, ac, tempA);
+ tempAL = tempA;
+
+ env->active_tc.HI[ac] = (tempAL & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = tempAL & MIPSDSP_LLO;
+}
+
+uint32_t helper_mul_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_mul_i16_i16(env, rsh, rth);
+ tempA = mipsdsp_mul_i16_i16(env, rsl, rtl);
+
+ rd = ((tempB & MIPSDSP_LO) << 16) | (tempA & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_mul_s_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_sat16_mul_i16_i16(env, rsh, rth);
+ tempA = mipsdsp_sat16_mul_i16_i16(env, rsl, rtl);
+
+ rd = ((tempB & MIPSDSP_LO) << 16) | (tempA & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_mulq_s_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl;
+ int32_t temp, tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_sat16_mul_q15_q15(env, rsh, rth);
+ tempA = mipsdsp_sat16_mul_q15_q15(env, rsl, rtl);
+ temp = ((tempB & MIPSDSP_LO) << 16) | (tempA & MIPSDSP_LO);
+ rd = temp;
+
+ return rd;
+}
+
+uint32_t helper_mulq_s_w(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ int32_t tempI;
+ int64_t tempL;
+
+ if ((rs == 0x80000000) && (rt == 0x80000000)) {
+ tempL = 0x7FFFFFFF00000000ull;
+ set_DSPControl_overflow_flag(env, 1, 21);
+ } else {
+ tempL = ((int64_t)rs * (int64_t)rt) << 1;
+ }
+ tempI = (tempL & MIPSDSP_LHI) >> 32;
+ rd = tempI;
+
+ return rd;
+}
+
+uint32_t helper_mulq_rs_w(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ int32_t tempI;
+ int64_t tempL;
+
+ if ((rs == 0x80000000) && (rt == 0x80000000)) {
+ tempL = 0x7FFFFFFF00000000ull;
+ set_DSPControl_overflow_flag(env, 1, 21);
+ } else {
+ tempL = ((int64_t)rs * (int64_t)rt) << 1;
+ tempL += 0x80000000;
+ }
+ tempI = (tempL & MIPSDSP_LHI) >> 32;
+ rd = tempI;
+
+ return rd;
+}
+
+void helper_mulsa_w_ph(CPUMIPSState *env, int ac, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl;
+ int32_t tempB, tempA;
+ int64_t dotp, acc, tempBL, tempAL;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = (int32_t)rsh * (int32_t)rth;
+ tempA = (int32_t)rsl * (int32_t)rtl;
+ tempBL = tempB;
+ tempAL = tempA;
+
+ dotp = tempBL - tempAL;
+ acc = ((int64_t)env->active_tc.HI[ac] << 32) | \
+ ((int64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
+ acc = acc + dotp;
+
+ env->active_tc.HI[ac] = (acc & MIPSDSP_LHI) >> 32;
+ env->active_tc.LO[ac] = acc & MIPSDSP_LLO;
+}
+
#undef MIPSDSP_LHI
#undef MIPSDSP_LLO
#undef MIPSDSP_HI
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 14c4574..bd6f3b5 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -376,4 +376,38 @@ DEF_HELPER_FLAGS_2(shrav_r_ph, TCG_CALL_CONST |
TCG_CALL_PURE, i32, i32, i32)
DEF_HELPER_FLAGS_2(shra_r_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, int, i32)
DEF_HELPER_FLAGS_2(shrav_r_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+/* DSP Multiply Sub-class insns */
+DEF_HELPER_FLAGS_3(muleu_s_ph_qbl, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(muleu_s_ph_qbr, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(mulq_rs_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(muleq_s_w_phl, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(muleq_s_w_phr, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_4(dpau_h_qbl, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpau_h_qbr, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpsu_h_qbl, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpsu_h_qbr, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpa_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpax_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpaq_s_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpaqx_s_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpaqx_sa_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dps_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpsx_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpsq_s_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpsqx_s_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpsqx_sa_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(mulsaq_s_w_ph, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpaq_sa_l_w, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(dpsq_sa_l_w, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(maq_s_w_phl, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(maq_s_w_phr, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(maq_sa_w_phl, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_4(maq_sa_w_phr, 0, void, env, int, i32, i32)
+DEF_HELPER_FLAGS_3(mul_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(mul_s_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(mulq_s_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(mulq_s_w, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(mulq_rs_w, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_4(mulsa_w_ph, 0, void, env, int, i32, i32)
+
#include "def-helper.h"
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 1c39246..69a6929 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -323,6 +323,10 @@ enum {
OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
/* MIPS DSP GPR-Based Shift Sub-class */
OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
+ /* MIPS DSP Multiply Sub-class insns */
+ /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
+ /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
+ OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
};
/* BSHFL opcodes */
@@ -376,6 +380,13 @@ enum {
OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
+ /* MIPS DSP Multiply Sub-class insns */
+ OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP,
+ OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
};
#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
@@ -394,6 +405,11 @@ enum {
OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
+ /* MIPS DSP Multiply Sub-class insns */
+ OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP,
+ OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP,
+ OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP,
};
#define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
@@ -453,6 +469,33 @@ enum {
OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP,
};
+#define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* MIPS DSP Multiply Sub-class insns */
+ OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP,
+ OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP,
+ OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
+};
+
/* Coprocessor 0 (rs field) */
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
@@ -12221,6 +12264,22 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx, int *is_branch)
case OPC_SUBQH_R_W:
gen_helper_subqh_r_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
break;
+ case OPC_MUL_PH:
+ gen_helper_mul_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MUL_S_PH:
+ gen_helper_mul_s_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULQ_S_W:
+ gen_helper_mulq_s_w(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULQ_RS_W:
+ gen_helper_mulq_rs_w(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
default:
is_mult_g_2e = 1;
break;
@@ -12385,6 +12444,30 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx, int *is_branch)
case OPC_RADDU_W_QB:
gen_helper_raddu_w_qb(cpu_gpr[rd], cpu_gpr[rs]);
break;
+ case OPC_MULEU_S_PH_QBL:
+ gen_helper_muleu_s_ph_qbl(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULEU_S_PH_QBR:
+ gen_helper_muleu_s_ph_qbr(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULQ_RS_PH:
+ gen_helper_mulq_rs_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULEQ_S_W_PHL:
+ gen_helper_muleq_s_w_phl(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULEQ_S_W_PHR:
+ gen_helper_muleq_s_w_phr(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MULQ_S_PH:
+ gen_helper_mulq_s_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
}
break;
case OPC_CMPU_EQ_QB_DSP:
@@ -12509,6 +12592,187 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx, int *is_branch)
tcg_temp_free(temp_rs);
break;
}
+ case OPC_DPA_W_PH_DSP:
+ op2 = MASK_DPA_W_PH(ctx->opcode);
+ switch (op2) {
+ case OPC_DPAU_H_QBL:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpau_h_qbl(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAU_H_QBR:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpau_h_qbr(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSU_H_QBL:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsu_h_qbl(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSU_H_QBR:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsu_h_qbr(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPA_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpa_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAX_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpax_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAQ_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpaq_s_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAQX_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpaqx_s_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAQX_SA_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpaqx_sa_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPS_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dps_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSX_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsx_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSQ_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsq_s_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSQX_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsqx_s_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSQX_SA_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsqx_sa_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MULSAQ_S_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_mulsaq_s_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPAQ_SA_L_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpaq_sa_l_w(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_DPSQ_SA_L_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_dpsq_sa_l_w(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MAQ_S_W_PHL:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_maq_s_w_phl(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MAQ_S_W_PHR:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_maq_s_w_phr(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MAQ_SA_W_PHL:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_maq_sa_w_phl(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MAQ_SA_W_PHR:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_maq_sa_w_phr(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_MULSA_W_PH:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_mulsa_w_ph(cpu_env, temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ }
+ break;
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
--
1.7.5.4
