On Wed, Jun 5, 2024 at 4:35 PM <frank.ch...@sifive.com> wrote: > > From: Frank Chang <frank.ch...@sifive.com> > > RISCVCPUImpliedExtsRule is created to store the implied rules. > 'is_misa' flag is used to distinguish whether the rule is derived > from the MISA or other extensions. > 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores > the offset of the extension defined in RISCVCPUConfig. 'ext' will also > serve as the key of the hash tables to look up the rule in the following > commit. > > Signed-off-by: Frank Chang <frank.ch...@sifive.com> > --- > target/riscv/cpu.c | 8 ++++++++ > target/riscv/cpu.h | 18 ++++++++++++++++++ > 2 files changed, 26 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cee6fc4a9a..c7e5cec7ef 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2242,6 +2242,14 @@ RISCVCPUProfile *riscv_profiles[] = { > NULL, > }; > > +RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = { > + NULL > +}; > + > +RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = { > + NULL > +}; > + > static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 1501868008..b5a036cf27 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -122,6 +122,24 @@ typedef enum { > EXT_STATUS_DIRTY, > } RISCVExtStatus; > > +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule; > + > +struct riscv_cpu_implied_exts_rule { > + /* Bitmask indicates the rule enabled status for the harts. */ > + uint64_t enabled;
I'm not clear why we need this Alistair > + /* True if this is a MISA implied rule. */ > + bool is_misa; > + /* ext is MISA bit if is_misa flag is true, else extension offset. */ > + const uint32_t ext; > + const uint32_t implied_misas; > + const uint32_t implied_exts[]; > +}; > + > +extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[]; > +extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[]; > + > +#define RISCV_IMPLIED_EXTS_RULE_END -1 > + > #define MMU_USER_IDX 3 > > #define MAX_RISCV_PMPS (16) > -- > 2.43.2 > >