On Mon, 10 Jun 2024 at 06:29, Sebastian Huber
<sebastian.hu...@embedded-brains.de> wrote:
>
> Fix the system bus interrupt line to CPU core assignment.
>
> Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
> ---
> hw/arm/xilinx_zynq.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index 7f7a3d23fb..c79661bbc1 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -252,10 +252,11 @@ static void zynq_init(MachineState *machine)
> zynq_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;
> sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL);
> for (n = 0; n < smp_cpus; n++) {
> + /* See "hw/intc/arm_gic.h" for the IRQ line association */
> DeviceState *cpudev = DEVICE(zynq_machine->cpu[n]);
> - sysbus_connect_irq(busdev, (2 * n) + 0,
> + sysbus_connect_irq(busdev, n,
> qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
> - sysbus_connect_irq(busdev, (2 * n) + 1,
> + sysbus_connect_irq(busdev, smp_cpus + n,
> qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
> }
Applied to target-arm.next, thanks.
-- PMM
