On Wed, May 15, 2024 at 6:03 PM Fea.Wang <fea.w...@sifive.com> wrote:
>
> Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH
> and HEDELEGH for exception codes 32-47 for reserving and exception codes
> 48-63 for custom use. Add the CSR number though the implementation is
> just reading zero and writing ignore. Besides, for accessing HEDELEGH, it
> should be controlled by mstateen0 'P1P13' bit.
>
> Signed-off-by: Fea.Wang <fea.w...@sifive.com>
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 2 ++
> target/riscv/csr.c | 31 +++++++++++++++++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 28bd3fb0b4..f888025c59 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -156,6 +156,8 @@
>
> /* 32-bit only */
> #define CSR_MSTATUSH 0x310
> +#define CSR_MEDELEGH 0x312
> +#define CSR_HEDELEGH 0x612
>
> /* Machine Trap Handling */
> #define CSR_MSCRATCH 0x340
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index bdbc8de0e2..c5ff40eed8 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3225,6 +3225,33 @@ static RISCVException write_hedeleg(CPURISCVState
> *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException read_hedelegh(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + RISCVException ret;
> + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
> + if (ret != RISCV_EXCP_NONE) {
> + return ret;
> + }
> +
> + /* Reserved, now read zero */
> + *val = 0;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException write_hedelegh(CPURISCVState *env, int csrno,
> + target_ulong val)
> +{
> + RISCVException ret;
> + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
> + if (ret != RISCV_EXCP_NONE) {
> + return ret;
> + }
> +
> + /* Reserved, now write ignore */
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException rmw_hvien64(CPURISCVState *env, int csrno,
> uint64_t *ret_val,
> uint64_t new_val, uint64_t wr_mask)
> @@ -4672,6 +4699,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
> write_mstatush },
> + [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore,
> + .min_priv_ver = PRIV_VERSION_1_13_0 },
> + [CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh,
> write_hedelegh,
> + .min_priv_ver = PRIV_VERSION_1_13_0 },
>
> /* Machine Trap Handling */
> [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch,
> --
> 2.34.1
>
>
