Hi Daniel, On Sat, Jun 1, 2024 at 2:52 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > Hi Atish, > > > I see that Rajnesh sent some patches that were built on top of this > work [1], and this series no longer applies neither to alistair's > risc-to-apply.next nor to master. > > If you could send a rebased version of this series that would be great. > >
Yes. I am planning to send revised series for counter delegation, Smcntrpmf and a few other miscellaneous fixes soon. > Thanks, > > > Daniel > > > > [1] > https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkan...@rivosinc.com/ > > > On 2/16/24 21:01, Atish Patra wrote: > > This series adds the counter delegation extension support. The counter > > delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA > > extensions. > > > > 1. S[m|s]csrind : The indirect CSR extension[1] which defines additional > > 5 ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitation of > > RISC-V CSR address space. > > 2. Smstateen: The stateen bit[60] controls the access to the registers > > indirectly via the above indirect registers. > > 3. Smcdeleg/Ssccfg: The counter delegation extensions[2] > > > > The counter delegation extension allows Supervisor mode to program the > > hpmevent and hpmcounters directly without needing the assistance from the > > M-mode via SBI calls. This results in a faster perf profiling and very > > few traps. This extension also introduces a scountinhibit CSR which allows > > to stop/start any counter directly from the S-mode. As the counter > > delegation extension potentially can have more than 100 CSRs, the > > specificaiton > > leverages the indirect CSR extension to save the precious CSR address range. > > > > Due to the dependancy of these extensions, the following extensions must be > > enabled to use the counter delegation feature in S-mode. > > > > "smstateen=true,sscofpmf=true,ssccfg=true,smcdeleg=true,smcsrind=true,sscsrind=true" > > > > This makes the qemu command line quite tedious. In stead of that, I think we > > can enable these features by default if there is no objection. > > > > The first 2 patches decouple the indirect CSR usage from AIA implementation > > while patch3 adds stateen bits validation for AIA. > > The PATCH4 implements indirect CSR extensions while remaining patches > > implement the counter delegation extensions. > > > > The Qemu patches can be found here: > > https://github.com/atishp04/qemu/tree/counter_delegation_rfc > > > > The opensbi patch can be found here: > > https://github.com/atishp04/opensbi/tree/counter_delegation_v1 > > > > The Linux kernel patches can be found here: > > https://github.com/atishp04/linux/tree/counter_delegation_rfc > > > > [1] https://github.com/riscv/riscv-indirect-csr-access > > [2] https://github.com/riscv/riscv-smcdeleg-ssccfg > > > > Atish Patra (1): > > target/riscv: Enable S*stateen bits for AIA > > > > Kaiwen Xue (7): > > target/riscv: Add properties for Indirect CSR Access extension > > target/riscv: Decouple AIA processing from xiselect and xireg > > target/riscv: Support generic CSR indirect access > > target/riscv: Add smcdeleg/ssccfg properties > > target/riscv: Add counter delegation definitions > > target/riscv: Add select value range check for counter delegation > > target/riscv: Add counter delegation/configuration support > > > > target/riscv/cpu.c | 8 + > > target/riscv/cpu.h | 1 + > > target/riscv/cpu_bits.h | 34 +- > > target/riscv/cpu_cfg.h | 4 + > > target/riscv/csr.c | 713 +++++++++++++++++++++++++++++++++++++--- > > target/riscv/machine.c | 1 + > > 6 files changed, 722 insertions(+), 39 deletions(-) > > > > -- > > 2.34.1 > >
