Re: [PATCH 1/4] target/riscv: Add zimop extension

Sat, 25 May 2024 17:34:20 -0700 

Hi Daniel,

On 2024/5/24 17:46, Daniel Henrique Barboza wrote:



On 5/22/24 03:29, LIU Zhiwei wrote:

Zimop extension defines an encoding space for 40 MOPs.The Zimop
extension defines 32 MOP instructions named MOP.R.n, where n is
an integer between 0 and 31, inclusive. The Zimop extension
additionally defines 8 MOP instructions named MOP.RR.n, where n
is an integer between 0 and 7.

These 40 MOPs initially are defined to simply write zero to x[rd],
but are designed to be redefined by later extensions to perform some
other action.

Signed-off-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
---
  target/riscv/cpu.c                          |  2 ++
  target/riscv/cpu_cfg.h                      |  1 +
  target/riscv/insn32.decode                  | 11 ++++++
  target/riscv/insn_trans/trans_rvzimop.c.inc | 37 +++++++++++++++++++++
  target/riscv/translate.c                    |  1 +
  5 files changed, 52 insertions(+)
  create mode 100644 target/riscv/insn_trans/trans_rvzimop.c.inc

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index eb1a2e7d6d..c1ac521142 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -175,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
+    ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_12_0, ext_zimop),


Shouldn't this be placed right after zihpm?


Yes. Thanks.


I didn't notice the strict order between extensions. And will fix this 
and other similar comments in other patches.


Zhiwei




    ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, 
ext_zihintpause),

    ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),

+    ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_12_0, ext_zimop),

    ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),


Thanks,

Daniel



      ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
      ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
      ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),

@@ -1463,6 +1464,7 @@ const RISCVCPUMultiExtConfig 
riscv_cpu_extensions[] = {

      MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
      MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
      MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
+    MULTI_EXT_CFG_BOOL("zimop", ext_zimop, false),
      MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
      MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
      MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index cb750154bd..b547fbba9d 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -71,6 +71,7 @@ struct RISCVCPUConfig {
      bool ext_zihintntl;
      bool ext_zihintpause;
      bool ext_zihpm;
+    bool ext_zimop;
      bool ext_ztso;
      bool ext_smstateen;
      bool ext_sstc;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f22df04cfd..972a1e8fd1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -38,6 +38,8 @@
  %imm_bs   30:2                   !function=ex_shift_3
  %imm_rnum 20:4
  %imm_z6   26:1 15:5
+%imm_mop5 30:1 26:2 20:2
+%imm_mop3 30:1 26:2
    # Argument sets:
  &empty
@@ -56,6 +58,8 @@
  &r2nfvm    vm rd rs1 nf
  &rnfvm     vm rd rs1 rs2 nf
  &k_aes     shamt rs2 rs1 rd
+&mop5 imm rd rs1
+&mop3 imm rd rs1 rs2
    # Formats 32:

  @r       .......   ..... ..... ... ..... ....... &r                
%rs2 %rs1 %rd

@@ -98,6 +102,9 @@

  @k_aes   .. ..... ..... .....  ... ..... ....... &k_aes 
shamt=%imm_bs   %rs2 %rs1 %rd
  @i_aes   .. ..... ..... .....  ... ..... ....... &i 
imm=%imm_rnum        %rs1 %rd
  +@mop5 . . .. .. .... .. ..... ... ..... ....... &mop5 
imm=%imm_mop5 %rd %rs1
+@mop3 . . .. .. . ..... ..... ... ..... ....... &mop3 imm=%imm_mop3 
%rd %rs1 %rs2

+
  # Formats 64:

  @sh5     .......  ..... .....  ... ..... ....... &shift 
shamt=%sh5      %rs1 %rd
  @@ -1010,3 +1017,7 @@ amocas_w    00101 . . ..... ..... 010 ..... 
0101111 @atom_st

  amocas_d    00101 . . ..... ..... 011 ..... 0101111 @atom_st
  # *** RV64 Zacas Standard Extension ***
  amocas_q    00101 . . ..... ..... 100 ..... 0101111 @atom_st
+
+# *** Zimop may-be-operation extension ***
+mop_r_n     1 . 00 .. 0111 .. ..... 100 ..... 0111011 @mop5
+mop_rr_n    1 . 00 .. 1 ..... ..... 100 ..... 0111011 @mop3

diff --git a/target/riscv/insn_trans/trans_rvzimop.c.inc 
b/target/riscv/insn_trans/trans_rvzimop.c.inc

new file mode 100644
index 0000000000..165aacd2b6
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzimop.c.inc
@@ -0,0 +1,37 @@
+/*
+ * RISC-V translation routines for May-Be-Operation(zimop).
+ *
+ * Copyright (c) 2024 Alibaba Group.
+ *

+ * This program is free software; you can redistribute it and/or 
modify it

+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *

+ * This program is distributed in the hope it will be useful, but 
WITHOUT
+ * ANY WARRANTY; without even the implied warranty of 
MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public 
License for

+ * more details.
+ *

+ * You should have received a copy of the GNU General Public License 
along with

+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZIMOP(ctx) do {           \
+    if (!ctx->cfg_ptr->ext_zimop) {       \
+        return false;                     \
+    }                                     \
+} while (0)
+
+static bool trans_mop_r_n(DisasContext *ctx, arg_mop_r_n *a)
+{
+    REQUIRE_ZIMOP(ctx);
+    gen_set_gpr(ctx, a->rd, ctx->zero);
+    return true;
+}
+
+static bool trans_mop_rr_n(DisasContext *ctx, arg_mop_rr_n *a)
+{
+    REQUIRE_ZIMOP(ctx);
+    gen_set_gpr(ctx, a->rd, ctx->zero);
+    return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2c27fd4ce1..77c6564834 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c

@@ -1097,6 +1097,7 @@ static uint32_t opcode_at(DisasContextBase 
*dcbase, target_ulong pc)

  #include "insn_trans/trans_rvzacas.c.inc"
  #include "insn_trans/trans_rvzawrs.c.inc"
  #include "insn_trans/trans_rvzicbo.c.inc"
+#include "insn_trans/trans_rvzimop.c.inc"
  #include "insn_trans/trans_rvzfa.c.inc"
  #include "insn_trans/trans_rvzfh.c.inc"
  #include "insn_trans/trans_rvk.c.inc"
























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