On Tue, 7 May 2024 at 14:00, Sebastian Huber
<sebastian.hu...@embedded-brains.de> wrote:
>
> According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
> Registers, GICD_ISPENDRn":
>
> "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each
> connected
> processor. This register holds the Set-pending bits for interrupts 0-31."
The commit message says it's only changing the handling of
setting the pending bit for a PPI, but...
> Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
> ---
> hw/intc/arm_gic.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index 4da5326ed6..20b3f701e0 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -1296,12 +1296,14 @@ static void gic_dist_writeb(void *opaque, hwaddr
> offset,
>
> for (i = 0; i < 8; i++) {
> if (value & (1 << i)) {
> + int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
> +
> if (s->security_extn && !attrs.secure &&
> !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
> continue; /* Ignore Non-secure access of Group0 IRQ */
> }
>
> - GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i));
> + GIC_DIST_SET_PENDING(irq + i, cm);
... the patch changes also the handling of set-pending for
SPIs (which previously were marked pending on the target CPU
and are now marked pending on all CPUs).
Looking back at the thread from your 2021 patch this was also
noted in that version as being wrong:
https://lore.kernel.org/qemu-devel/20210725080817.ivlkutnow7soj...@sekoia-pc.home.lmichel.fr/
PS: for multi-patch patches please can you send also a cover
letter? Our automated tooling gets confused if there isn't one.
It looks also like you sent these respins of these patches as
followups to the thread of the original patch you sent back in
2021. Can you send new versions of patches as their own threads,
please (and with a "PATCH v2" (v3, etc) tag if they're respins?
thanks
-- PMM
