On Tue, Apr 30, 2024 at 5:29 AM Atish Patra <ati...@rivosinc.com> wrote:
>
> scounteren/hcountern are also WARL registers similar to mcountern.
> Only set the bits for the available counters during the write to
> preserve the WARL behavior.
>
> Signed-off-by: Atish Patra <ati...@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 68ca31aff47d..a01911541d67 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2843,7 +2843,11 @@ static RISCVException read_scounteren(CPURISCVState
> *env, int csrno,
> static RISCVException write_scounteren(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - env->scounteren = val;
> + RISCVCPU *cpu = env_archcpu(env);
> +
> + /* WARL register - disable unavailable counters */
> + env->scounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY |
> COUNTEREN_TM |
> + COUNTEREN_IR);
> return RISCV_EXCP_NONE;
> }
>
> @@ -3475,7 +3479,11 @@ static RISCVException read_hcounteren(CPURISCVState
> *env, int csrno,
> static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - env->hcounteren = val;
> + RISCVCPU *cpu = env_archcpu(env);
> +
> + /* WARL register - disable unavailable counters */
> + env->hcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY |
> COUNTEREN_TM |
> + COUNTEREN_IR);
> return RISCV_EXCP_NONE;
> }
>
>
> --
> 2.34.1
>
>
