On Tue, 9 Apr 2024 at 10:58, tugouxp <13824125...@163.com> wrote: > How does the qemu emulate the target that support "atomic" ISA, such as > riscv "amo" instruction on host machine that does NOT support atomic > instructions ? > is this scenario happends?
All hosts that can run QEMU support at least some atomic instructions. Where possible we use the host atomic operations to provide the necessary atomicity guarantees that a guest instruction must have. For cases where we can't do that (eg where the guest needs an atomic 16-byte store but the host doesn't have one), we arrange to pause execution of all the other guest vCPU threads, do the thing that must be atomic, and then let everything resume. thanks -- PMM
