On 19/03/24, Philippe Mathieu-Daudé wrote:
> The Exception Address Register is 64-bit wide.
> User emulation only access the 32 lower bits.
>
> Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
> ---
> target/microblaze/cpu.h | 2 +-
> linux-user/elfload.c | 2 +-
> target/microblaze/gdbstub.c | 2 +-
> target/microblaze/translate.c | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index c3e2aba0ec..a9f93b37b7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -251,7 +251,7 @@ struct CPUArchState {
> uint32_t pc;
> uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */
> uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */
> - target_ulong ear;
> + uint64_t ear;
> uint32_t esr;
> uint32_t fsr;
> uint32_t btr;
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 60cf55b36c..4612aef95a 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1498,7 +1498,7 @@ static void elf_core_copy_regs(target_elf_gregset_t
> *regs, const CPUMBState *env
> (*regs)[pos++] = tswapreg(env->pc);
> (*regs)[pos++] = tswapreg(mb_cpu_read_msr(env));
> (*regs)[pos++] = 0;
> - (*regs)[pos++] = tswapreg(env->ear);
> + (*regs)[pos++] = tswapreg((uint32_t)env->ear);
As far as I can tell env->ear is never written to from TCG so we
shouldn't have any problems w. endian mismatch between guest/host,
right?
Anyway,
Reviewed-by: Anton Johansson <a...@rev.ng>
