Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
target/xtensa/cpu.h | 70 ---------------------------------------------
target/xtensa/cpu.c | 69 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+), 70 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3826b779e4..2b6f2bdea7 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -734,76 +734,6 @@ static inline uint32_t
xtensa_replicate_windowstart(CPUXtensaState *env)
#include "exec/cpu-all.h"
-#define TARGET_HAS_CPU_GET_TB_CPU_STATE
-
-static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = 0;
- *flags |= xtensa_get_ring(env);
- if (env->sregs[PS] & PS_EXCM) {
- *flags |= XTENSA_TBFLAG_EXCM;
- } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
- target_ulong lend_dist =
- env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
-
- /*
- * 0 in the csbase_lend field means that there may not be a loopback
- * for any instruction that starts inside this page. Any other value
- * means that an instruction that ends at this offset from the page
- * start may loop back and will need loopback code to be generated.
- *
- * lend_dist is 0 when LEND points to the start of the page, but
- * no instruction that starts inside this page may end at offset 0,
- * so it's still correct.
- *
- * When an instruction ends at a page boundary it may only start in
- * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
- * for the TB that contains this instruction.
- */
- if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size)
{
- target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
-
- *cs_base = lend_dist;
- if (lbeg_off < 256) {
- *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
- }
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
- (env->sregs[LITBASE] & 1)) {
- *flags |= XTENSA_TBFLAG_LITBASE;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
- if (xtensa_get_cintlevel(env) < env->config->debug_level) {
- *flags |= XTENSA_TBFLAG_DEBUG;
- }
- if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
- *flags |= XTENSA_TBFLAG_ICOUNT;
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
- *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
- (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
- uint32_t windowstart = xtensa_replicate_windowstart(env) >>
- (env->sregs[WINDOW_BASE] + 1);
- uint32_t w = ctz32(windowstart | 0x8);
-
- *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
- *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
- PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
- } else {
- *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
- }
- if (env->yield_needed) {
- *flags |= XTENSA_TBFLAG_YIELD;
- }
-}
-
XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
Clock *cpu_refclk);
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 875cf843c9..35c66432a1 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -63,6 +63,74 @@ static void xtensa_restore_state_to_opc(CPUState *cs,
cpu->env.pc = data[0];
}
+static void xtensa_get_cpu_state(CPUXtensaState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = 0;
+ *flags |= xtensa_get_ring(env);
+ if (env->sregs[PS] & PS_EXCM) {
+ *flags |= XTENSA_TBFLAG_EXCM;
+ } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
+ target_ulong lend_dist =
+ env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
+
+ /*
+ * 0 in the csbase_lend field means that there may not be a loopback
+ * for any instruction that starts inside this page. Any other value
+ * means that an instruction that ends at this offset from the page
+ * start may loop back and will need loopback code to be generated.
+ *
+ * lend_dist is 0 when LEND points to the start of the page, but
+ * no instruction that starts inside this page may end at offset 0,
+ * so it's still correct.
+ *
+ * When an instruction ends at a page boundary it may only start in
+ * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
+ * for the TB that contains this instruction.
+ */
+ if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size)
{
+ target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
+
+ *cs_base = lend_dist;
+ if (lbeg_off < 256) {
+ *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
+ }
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
+ (env->sregs[LITBASE] & 1)) {
+ *flags |= XTENSA_TBFLAG_LITBASE;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
+ if (xtensa_get_cintlevel(env) < env->config->debug_level) {
+ *flags |= XTENSA_TBFLAG_DEBUG;
+ }
+ if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
+ *flags |= XTENSA_TBFLAG_ICOUNT;
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
+ *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
+ (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
+ uint32_t windowstart = xtensa_replicate_windowstart(env) >>
+ (env->sregs[WINDOW_BASE] + 1);
+ uint32_t w = ctz32(windowstart | 0x8);
+
+ *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
+ *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
+ PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
+ } else {
+ *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
+ }
+ if (env->yield_needed) {
+ *flags |= XTENSA_TBFLAG_YIELD;
+ }
+}
+
static bool xtensa_cpu_has_work(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
@@ -230,6 +298,7 @@ static const TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
.debug_excp_handler = xtensa_breakpoint_handler,
.restore_state_to_opc = xtensa_restore_state_to_opc,
+ .get_cpu_state = xtensa_get_cpu_state,
#ifndef CONFIG_USER_ONLY
.tlb_fill = xtensa_cpu_tlb_fill,
--
2.41.0
