On Tue, Mar 12, 2024 at 9:32 PM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > Commit 3b8022269c added the capability of named features/profile > extensions to be added in riscv,isa. To do that we had to assign priv > versions for each one of them in isa_edata_arr[]. But this resulted in a > side-effect: vendor CPUs that aren't running priv_version_latest started > to experience warnings for these profile extensions [1]: > > | $ qemu-system-riscv32 -M sifive_e > | qemu-system-riscv32: warning: disabling zic64b extension for hart > 0x00000000 because privilege spec version does not match > | qemu-system-riscv32: warning: disabling ziccamoa extension for > hart 0x00000000 because privilege spec version does not match > > This is benign as far as the CPU behavior is concerned since disabling > both extensions is a no-op (aside from riscv,isa). But the warnings are > unpleasant to deal with, especially because we're sending user warnings > for extensions that users can't enable/disable. > > Instead of enabling all named features all the time, separate them by > priv version. During finalize() time, after we decided which > priv_version the CPU is running, enable/disable all the named extensions > based on the priv spec chosen. This will be enough for a bug fix, but as > a future work we should look into how we can name these extensions in a > way that we don't need an explicit ext_name => priv_ver as we're doing > here. > > The named extensions being added in isa_edata_arr[] that will be > enabled/disabled based solely on priv version can be removed from > riscv_cpu_named_features[]. 'zic64b' is an extension that can be > disabled based on block sizes so it'll retain its own flag and entry. > > [1] https://lists.gnu.org/archive/html/qemu-devel/2024-03/msg02592.html > > Reported-by: Clément Chigot <chi...@adacore.com> > Fixes: 3b8022269c ("target/riscv: add riscv,isa to named features") > Suggested-by: Andrew Jones <ajo...@ventanamicro.com> > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > --- > target/riscv/cpu.c | 40 +++++++++----------------------------- > target/riscv/cpu_cfg.h | 8 +++++--- > target/riscv/tcg/tcg-cpu.c | 14 ++++++++++--- > 3 files changed, 25 insertions(+), 37 deletions(-)
Thanks for the quick patch ! Tested-by: Clément Chigot <chi...@adacore.com>
