This patch adds a new device STM32L4x5 GPIO device and is part of a series implementing the STM32L4x5 with a few peripherals.
Changes from v6 : - rebasing on main - removing QTest `clock_enable()` as it isn't actually a GPIO test Changes from v5 : - deduplicating macro constant `GPIO_NUM_PINS` that was defined both in stm32l4x5_syscfg.h and stm32l4x5_gpio.h - moving definition of constant `NUM_GPIOS` from syscfg.h to gpio.h - soc.c : replacing a hardcoded 16 by the correct `GPIO_NUM_PINS` Changes from v4 : - gpio.c : use helpers `is_pull_up()`, `is_pull_down()`, `is_output()` for more clarity - gpio.c : correct `update_gpio_idr()` in case of open-drain pin set to 1 in ODR and set to 0 externally - gpio.c : rename `get_gpio_pins_to_disconnect()` to `get_gpio_pinmask_to_disconnect()` and associated comments - gpio.c : correct coding style issues (alignment and declaration) - soc.c : unite structs `gpio_addr` and `stm32l4x5_gpio_initval` Changes from v3 : - replacing occurences of '16' with the correct macro `GPIO_NUM_PINS` - updating copyright year - rebasing on latest version of STM32L4x5 RCC Changes from v2 : - correct memory leaks caused by re-assigning a `g_autofree` pointer without freeing it - gpio-test : test that reset values (and not just initialization values) are correct, correct `stm32l4x5_gpio_reset()` accordingly - adding a `clock-freq-hz` object property to test that enabling GPIO clock in RCC sets the GPIO clocks Changes from v1 : - replacing test GPIO register `DISCONNECTED_PINS` with an object property accessed using `qtest_qmp()` in the qtest (through helpers `get_disconnected_pins()` and `disconnect_all_pins()`) - removing GPIO subclasses and storing MODER, OSPEEDR and PUPDR reset values in properties - adding a `name` property and using it for more lisible traces - using `g_strdup_printf()` to facilitate setting irqs in the qtest, and initializing GPIO children in soc_initfn Changes from RFC v1 : - `stm32l4x5-gpio-test.c` : correct typos, make the test generic, add a test for bitwise writing in register ODR - `stm32l4x5_soc.c` : connect gpios to their clock, use an array of GpioState - `stm32l4x5_gpio.c` : correct comments in `update_gpio_idr()`, correct `get_gpio_pins_to_disconnect()`, correct `stm32l4x5_gpio_init()` and initialize the clock, add a realize function - update MAINAINERS Signed-off-by: Arnaud Minier <arnaud.min...@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.var...@telecom-paris.fr> Inès Varhol (3): hw/gpio: Implement STM32L4x5 GPIO hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC tests/qtest: Add STM32L4x5 GPIO QTest testcase MAINTAINERS | 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- include/hw/arm/stm32l4x5_soc.h | 2 + include/hw/gpio/stm32l4x5_gpio.h | 71 ++++ include/hw/misc/stm32l4x5_syscfg.h | 3 +- hw/arm/stm32l4x5_soc.c | 71 +++- hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++ hw/misc/stm32l4x5_syscfg.c | 1 + tests/qtest/stm32l4x5_gpio-test.c | 551 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 3 +- hw/gpio/Kconfig | 3 + hw/gpio/meson.build | 1 + hw/gpio/trace-events | 6 + tests/qtest/meson.build | 3 +- 14 files changed, 1175 insertions(+), 20 deletions(-) create mode 100644 include/hw/gpio/stm32l4x5_gpio.h create mode 100644 hw/gpio/stm32l4x5_gpio.c create mode 100644 tests/qtest/stm32l4x5_gpio-test.c -- 2.43.2
