Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/sparc/helper.h | 2 ++
target/sparc/translate.c | 4 ++++
target/sparc/vis_helper.c | 11 +++++++++++
target/sparc/insns.decode | 2 ++
4 files changed, 19 insertions(+)
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 56daf2ad01..9b642fd74b 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -130,6 +130,8 @@ DEF_HELPER_FLAGS_2(fcmpeq8, TCG_CALL_NO_RWG_SE, i64, i64,
i64)
DEF_HELPER_FLAGS_2(fcmpne8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fcmpule8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fcmpugt8, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(xmulx, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(xmulxhi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#endif
#undef VIS_HELPER
#undef VIS_CMPHELPER
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2d697d2020..f8db98c32f 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -91,6 +91,8 @@
# define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL; })
# define gen_helper_fxtos ({ qemu_build_not_reached(); NULL; })
# define gen_helper_pdist ({ qemu_build_not_reached(); NULL; })
+# define gen_helper_xmulx ({ qemu_build_not_reached(); NULL; })
+# define gen_helper_xmulxhi ({ qemu_build_not_reached(); NULL; })
# define MAXTL_MASK 0
#endif
@@ -5081,6 +5083,8 @@ TRANS(FPCMPULE8, VIS3B, do_rdd, a, gen_helper_fcmpule8)
TRANS(FPCMPUGT8, VIS3B, do_rdd, a, gen_helper_fcmpugt8)
TRANS(PDISTN, VIS3, do_rdd, a, gen_op_pdistn)
+TRANS(XMULX, VIS3, do_rdd, a, gen_helper_xmulx)
+TRANS(XMULXHI, VIS3, do_rdd, a, gen_helper_xmulxhi)
static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c
index 8675ac64b3..387acb3855 100644
--- a/target/sparc/vis_helper.c
+++ b/target/sparc/vis_helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
+#include "crypto/clmul.h"
/* This function uses non-native bit order */
#define GET_FIELD(X, FROM, TO) \
@@ -492,3 +493,13 @@ uint64_t helper_fslas32(uint64_t src1, uint64_t src2)
return r.ll;
}
+
+uint64_t helper_xmulx(uint64_t src1, uint64_t src2)
+{
+ return int128_getlo(clmul_64(src1, src2));
+}
+
+uint64_t helper_xmulxhi(uint64_t src1, uint64_t src2)
+{
+ return int128_gethi(clmul_64(src1, src2));
+}
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 0cd1cffe18..54ba329440 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -391,6 +391,8 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
ADDXCcc 10 ..... 110110 ..... 0 0001 0011 ..... @r_r_r
UMULXHI 10 ..... 110110 ..... 0 0001 0110 ..... @r_r_r
LZCNT 10 ..... 110110 00000 0 0001 0111 ..... @r_r2
+ XMULX 10 ..... 110110 ..... 1 0001 0101 ..... @r_r_r
+ XMULXHI 10 ..... 110110 ..... 1 0001 0110 ..... @r_r_r
ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r
ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r
--
2.34.1
