Hi Philippe, Thanks for the heads up. Sorry I didn't check for this before sending out my patch. I'll track this in Demin's thread.
> -----原始邮件----- > 发件人: "Philippe Mathieu-Daudé" <phi...@linaro.org> > 发送时间: 2024-03-01 23:51:03 (星期五) > 收件人: SiHuaN <liyong...@iscas.ac.cn>, qemu-devel@nongnu.org > 抄送: "demin.han" <demin....@starfivetech.com>, qemu-riscv <qemu-ri...@nongnu.org>, "Daniel Henrique Barboza" <dbarb...@ventanamicro.com> > 主题: Re: [PATCH] Fix unexpected Illegal instruction error on RISC-V. > > Hi SiHuaN, > > On 1/3/24 15:55, SiHuaN wrote: > > Avoid right-shifting by a negative number of bits when lmul is 8. > > FYI Demin posted a similar patch, see: > https://lore.kernel.org/qemu-devel/20240225174114.5298-1-demin....@starfivetech.com/ > > > Signed-off-by: SiHuaN <liyong...@iscas.ac.cn> > > --- > > target/riscv/vector_helper.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > > index 84cec73eb2..f0158ea237 100644 > > --- a/target/riscv/vector_helper.c > > +++ b/target/riscv/vector_helper.c > > @@ -53,10 +53,11 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > > * VLEN * LMUL >= SEW > > * VLEN >> (8 - lmul) >= sew > > * (vlenb << 3) >> (8 - lmul) >= sew > > + * Considering that lmul may be 8, the following form cannot be used. > > * vlenb >> (8 - 3 - lmul) >= sew > > */ > > if (vlmul == 4 || > > - cpu->cfg.vlenb >> (8 - 3 - vlmul) < sew) { > > + (cpu->cfg.vlenb << 3) >> (8 - vlmul) < sew) { > > vill = true; > > } > > } </liyong...@iscas.ac.cn></dbarb...@ventanamicro.com></qemu-ri...@nongnu.org></demin....@starfivetech.com></liyong...@iscas.ac.cn></phi...@linaro.org>