On Tue, Feb 20, 2024 at 2:10 AM X512 via <qemu-devel@nongnu.org> wrote:
>
> MCFG segments should point to PCI configuration range, not BAR MMIO.
>
> Signed-off-by: Ilya Chugin <danger_m...@list.ru>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>   hw/riscv/virt-acpi-build.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index fb8baf64f6..fe01b626ea 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -558,8 +558,8 @@ static void virt_acpi_build(RISCVVirtState *s,
> AcpiBuildTables *tables)
>       acpi_add_table(table_offsets, tables_blob);
>       {
>           AcpiMcfgInfo mcfg = {
> -           .base = s->memmap[VIRT_PCIE_MMIO].base,
> -           .size = s->memmap[VIRT_PCIE_MMIO].size,
> +           .base = s->memmap[VIRT_PCIE_ECAM].base,
> +           .size = s->memmap[VIRT_PCIE_ECAM].size,
>           };
>           build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id,
>                      s->oem_table_id);
> --
> 2.42.1
>
>

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