Instantiate TYPE_ICH9_SMB_DEVICE in TYPE_ICH9_SOUTHBRIDGE.
Since the PC machines can disable SMBus (see the
PC_MACHINE_SMBUS dynamic property), add the 'smbus-enabled'
property to disable it.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
include/hw/southbridge/ich9.h | 32 --------------------------------
hw/i2c/smbus_ich9.c | 29 ++++++++++++++++++++++++++++-
hw/i386/pc_q35.c | 10 ++--------
hw/southbridge/ich9.c | 21 +++++++++++++++++++++
hw/southbridge/Kconfig | 1 +
5 files changed, 52 insertions(+), 41 deletions(-)
diff --git a/include/hw/southbridge/ich9.h b/include/hw/southbridge/ich9.h
index ac7f9f4ff5..d4b299bf3c 100644
--- a/include/hw/southbridge/ich9.h
+++ b/include/hw/southbridge/ich9.h
@@ -173,38 +173,6 @@ struct ICH9LPCState {
#define ICH9_APM_ACPI_ENABLE 0x2
#define ICH9_APM_ACPI_DISABLE 0x3
-
-/* D31:F3 SMBus controller */
-#define TYPE_ICH9_SMB_DEVICE "ICH9-SMB"
-
-#define ICH9_A2_SMB_REVISION 0x02
-#define ICH9_SMB_PI 0x00
-
-#define ICH9_SMB_SMBMBAR0 0x10
-#define ICH9_SMB_SMBMBAR1 0x14
-#define ICH9_SMB_SMBM_BAR 0
-#define ICH9_SMB_SMBM_SIZE (1 << 8)
-#define ICH9_SMB_SMB_BASE 0x20
-#define ICH9_SMB_SMB_BASE_BAR 4
-#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
-#define ICH9_SMB_HOSTC 0x40
-#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
-#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
-#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
-#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
-
-/* D31:F3 SMBus I/O and memory mapped I/O registers */
-#define ICH9_SMB_DEV 31
-#define ICH9_SMB_FUNC 3
-
-#define ICH9_SMB_HST_STS 0x00
-#define ICH9_SMB_HST_CNT 0x02
-#define ICH9_SMB_HST_CMD 0x03
-#define ICH9_SMB_XMIT_SLVA 0x04
-#define ICH9_SMB_HST_D0 0x05
-#define ICH9_SMB_HST_D1 0x06
-#define ICH9_SMB_HOST_BLOCK_DB 0x07
-
#define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features"
/* bit positions used in fw_cfg SMI feature negotiation */
diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c
index 3980bca4c5..2c18278090 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -26,10 +26,37 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
-#include "hw/southbridge/ich9.h"
#include "qom/object.h"
#include "hw/acpi/acpi_aml_interface.h"
+/* D31:F3 SMBus controller */
+
+#define ICH9_A2_SMB_REVISION 0x02
+#define ICH9_SMB_PI 0x00
+
+#define ICH9_SMB_SMBMBAR0 0x10
+#define ICH9_SMB_SMBMBAR1 0x14
+#define ICH9_SMB_SMBM_BAR 0
+#define ICH9_SMB_SMBM_SIZE (1 << 8)
+#define ICH9_SMB_SMB_BASE 0x20
+#define ICH9_SMB_SMB_BASE_BAR 4
+#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
+#define ICH9_SMB_HOSTC 0x40
+#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
+#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
+#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
+#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
+
+/* D31:F3 SMBus I/O and memory mapped I/O registers */
+
+#define ICH9_SMB_HST_STS 0x00
+#define ICH9_SMB_HST_CNT 0x02
+#define ICH9_SMB_HST_CMD 0x03
+#define ICH9_SMB_XMIT_SLVA 0x04
+#define ICH9_SMB_HST_D0 0x05
+#define ICH9_SMB_HST_D1 0x06
+#define ICH9_SMB_HOST_BLOCK_DB 0x07
+
static bool ich9_vmstate_need_smbus(void *opaque, int version_id)
{
return pm_smbus_vmstate_needed();
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 060358d449..7f6ced8a6e 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -236,6 +236,7 @@ static void pc_q35_init(MachineState *machine)
OBJECT(host_bus), &error_abort);
qdev_prop_set_bit(ich9, "d2p-enabled", false);
qdev_prop_set_bit(ich9, "sata-enabled", pcms->sata_enabled);
+ qdev_prop_set_bit(ich9, "smbus-enabled", pcms->smbus_enabled);
qdev_realize_and_unref(ich9, NULL, &error_fatal);
/* irq lines */
@@ -309,15 +310,8 @@ static void pc_q35_init(MachineState *machine)
}
if (pcms->smbus_enabled) {
- PCIDevice *smb;
-
+ pcms->smbus = I2C_BUS(qdev_get_child_bus(ich9, "i2c"));
/* TODO: Populate SPD eeprom data. */
- smb = pci_create_simple_multifunction(host_bus,
- PCI_DEVFN(ICH9_SMB_DEV,
- ICH9_SMB_FUNC),
- TYPE_ICH9_SMB_DEVICE);
- pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c"));
-
smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
}
diff --git a/hw/southbridge/ich9.c b/hw/southbridge/ich9.c
index 233dc1c5d7..4d2c298666 100644
--- a/hw/southbridge/ich9.c
+++ b/hw/southbridge/ich9.c
@@ -15,9 +15,11 @@
#include "hw/pci-bridge/ich_dmi_pci.h"
#include "hw/ide/ahci-pci.h"
#include "hw/ide.h"
+#include "hw/i2c/smbus_ich9.h"
#define ICH9_D2P_DEVFN PCI_DEVFN(30, 0)
#define ICH9_SATA1_DEVFN PCI_DEVFN(31, 2)
+#define ICH9_SMB_DEVFN PCI_DEVFN(31, 3)
#define SATA_PORTS 6
@@ -26,10 +28,12 @@ struct ICH9State {
I82801b11Bridge d2p;
AHCIPCIState sata0;
+ ICH9SMBState smb;
PCIBus *pci_bus;
bool d2p_enabled;
bool sata_enabled;
+ bool smbus_enabled;
};
static Property ich9_props[] = {
@@ -37,6 +41,7 @@ static Property ich9_props[] = {
TYPE_PCIE_BUS, PCIBus *),
DEFINE_PROP_BOOL("d2p-enabled", ICH9State, d2p_enabled, true),
DEFINE_PROP_BOOL("sata-enabled", ICH9State, sata_enabled, true),
+ DEFINE_PROP_BOOL("smbus-enabled", ICH9State, smbus_enabled, true),
DEFINE_PROP_END_OF_LIST(),
};
@@ -79,6 +84,18 @@ static bool ich9_realize_sata(ICH9State *s, Error **errp)
return true;
}
+static bool ich9_realize_smbus(ICH9State *s, Error **errp)
+{
+ object_initialize_child(OBJECT(s), "smb", &s->smb, TYPE_ICH9_SMB_DEVICE);
+ qdev_prop_set_int32(DEVICE(&s->smb), "addr", ICH9_SMB_DEVFN);
+ if (!qdev_realize(DEVICE(&s->smb), BUS(s->pci_bus), errp)) {
+ return false;
+ }
+ object_property_add_alias(OBJECT(s), "i2c", OBJECT(&s->smb), "i2c");
+
+ return true;
+}
+
static void ich9_init(Object *obj)
{
}
@@ -99,6 +116,10 @@ static void ich9_realize(DeviceState *dev, Error **errp)
if (s->sata_enabled && !ich9_realize_sata(s, errp)) {
return;
}
+
+ if (s->smbus_enabled && !ich9_realize_smbus(s, errp)) {
+ return;
+ }
}
static void ich9_class_init(ObjectClass *klass, void *data)
diff --git a/hw/southbridge/Kconfig b/hw/southbridge/Kconfig
index f806033d48..03e89a55d1 100644
--- a/hw/southbridge/Kconfig
+++ b/hw/southbridge/Kconfig
@@ -5,3 +5,4 @@ config ICH9
depends on PCI_EXPRESS
imply I82801B11
select AHCI_ICH9
+ select ACPI_ICH9
--
2.41.0
