There were no CPU models, so make TYPE_MICROBLAZE_CPU non-abstract. Signed-off-by: Andreas Färber <afaer...@suse.de> --- Makefile.target | 1 + target-microblaze/cpu-qom.h | 71 ++++++++++++++++++++++++ target-microblaze/cpu.c | 120 +++++++++++++++++++++++++++++++++++++++++ target-microblaze/cpu.h | 2 + target-microblaze/translate.c | 58 ++------------------ 5 files changed, 199 insertions(+), 53 deletions(-) create mode 100644 target-microblaze/cpu-qom.h create mode 100644 target-microblaze/cpu.c
diff --git a/Makefile.target b/Makefile.target index 8c8f4a8..82171ca 100644 --- a/Makefile.target +++ b/Makefile.target @@ -92,6 +92,7 @@ libobj-$(TARGET_ARM) += cpu.o libobj-$(TARGET_CRIS) += cpu.o libobj-$(TARGET_LM32) += cpu.o libobj-$(TARGET_M68K) += cpu.o +libobj-$(TARGET_MICROBLAZE) += cpu.o ifeq ($(TARGET_BASE_ARCH), mips) libobj-y += cpu.o endif diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h new file mode 100644 index 0000000..576be10 --- /dev/null +++ b/target-microblaze/cpu-qom.h @@ -0,0 +1,71 @@ +/* + * QEMU MicroBlaze CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * <http://www.gnu.org/licenses/lgpl-2.1.html> + */ +#ifndef QEMU_MICROBLAZE_CPU_QOM_H +#define QEMU_MICROBLAZE_CPU_QOM_H + +#include "qemu/cpu.h" +#include "cpu.h" + +#define TYPE_MICROBLAZE_CPU "microblaze-cpu" + +#define MICROBLAZE_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(MicroBlazeCPUClass, (klass), TYPE_MICROBLAZE_CPU) +#define MICROBLAZE_CPU(obj) \ + OBJECT_CHECK(MicroBlazeCPU, (obj), TYPE_MICROBLAZE_CPU) +#define MICROBLAZE_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MicroBlazeCPUClass, (obj), TYPE_MICROBLAZE_CPU) + +/** + * MicroBlazeCPUClass: + * @parent_reset: The parent class' reset handler. + * + * A MicroBlaze CPU model. + */ +typedef struct MicroBlazeCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + void (*parent_reset)(CPUState *cpu); +} MicroBlazeCPUClass; + +/** + * MicroBlazeCPU: + * @env: Legacy CPU state. + * + * A MicroBlaze CPU. + */ +typedef struct MicroBlazeCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUMBState env; +} MicroBlazeCPU; + +static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) +{ + return MICROBLAZE_CPU(container_of(env, MicroBlazeCPU, env)); +} + +#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e)) + + +#endif diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c new file mode 100644 index 0000000..ae55376 --- /dev/null +++ b/target-microblaze/cpu.c @@ -0,0 +1,120 @@ +/* + * QEMU MicroBlaze CPU + * + * Copyright (c) 2009 Edgar E. Iglesias. + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * <http://www.gnu.org/licenses/lgpl-2.1.html> + */ + +#include "cpu-qom.h" +#include "qemu-common.h" + +static void mb_cpu_reset(CPUState *c) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(c); + MicroBlazeCPUClass *klass = MICROBLAZE_CPU_GET_CLASS(cpu); + CPUMBState *env = &cpu->env; + + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); + log_cpu_state(env, 0); + } + + klass->parent_reset(c); + + memset(env, 0, offsetof(CPUMBState, breakpoints)); + tlb_flush(env, 1); + + /* Disable stack protector. */ + env->shr = ~0; + + env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ + | PVR0_USE_BARREL_MASK \ + | PVR0_USE_DIV_MASK \ + | PVR0_USE_HW_MUL_MASK \ + | PVR0_USE_EXC_MASK \ + | PVR0_USE_ICACHE_MASK \ + | PVR0_USE_DCACHE_MASK \ + | PVR0_USE_MMU \ + | (0xb << 8); + env->pvr.regs[2] = PVR2_D_OPB_MASK \ + | PVR2_D_LMB_MASK \ + | PVR2_I_OPB_MASK \ + | PVR2_I_LMB_MASK \ + | PVR2_USE_MSR_INSTR \ + | PVR2_USE_PCMP_INSTR \ + | PVR2_USE_BARREL_MASK \ + | PVR2_USE_DIV_MASK \ + | PVR2_USE_HW_MUL_MASK \ + | PVR2_USE_MUL64_MASK \ + | PVR2_USE_FPU_MASK \ + | PVR2_USE_FPU2_MASK \ + | PVR2_FPU_EXC_MASK \ + | 0; + env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ + env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); + +#if defined(CONFIG_USER_ONLY) + /* Start in user mode with interrupts enabled. */ + env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; + env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ +#else + env->sregs[SR_MSR] = 0; + mmu_init(&env->mmu); + env->mmu.c_mmu = 3; + env->mmu.c_mmu_tlb_access = 3; + env->mmu.c_mmu_zones = 16; +#endif +} + +static void mb_cpu_initfn(Object *obj) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); + CPUMBState *env = &cpu->env; + + memset(env, 0, sizeof(*env)); + cpu_exec_init(env); + env->cpu_model_str = object_get_typename(obj); + + set_float_rounding_mode(float_round_nearest_even, &env->fp_status); + + cpu_reset(CPU(cpu)); +} + +static void mb_cpu_class_init(ObjectClass *klass, void *data) +{ + CPUClass *cpu_class = CPU_CLASS(klass); + MicroBlazeCPUClass *k = MICROBLAZE_CPU_CLASS(klass); + + k->parent_reset = cpu_class->reset; + cpu_class->reset = mb_cpu_reset; +} + +static const TypeInfo mb_cpu_type_info = { + .name = TYPE_MICROBLAZE_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(MicroBlazeCPU), + .instance_init = mb_cpu_initfn, + .class_size = sizeof(MicroBlazeCPUClass), + .class_init = mb_cpu_class_init, +}; + +static void mb_cpu_register_types(void) +{ + type_register_static(&mb_cpu_type_info); +} + +type_init(mb_cpu_register_types) diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 3b52421..279c143 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -266,6 +266,8 @@ typedef struct CPUMBState { CPU_COMMON } CPUMBState; +#include "cpu-qom.h" + CPUMBState *cpu_mb_init(const char *cpu_model); int cpu_mb_exec(CPUMBState *s); void cpu_mb_close(CPUMBState *s); diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 64cbfb8..b188f6c 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1888,18 +1888,17 @@ void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, "\n\n"); } -CPUMBState *cpu_mb_init (const char *cpu_model) +CPUMBState *cpu_mb_init(const char *cpu_model) { + MicroBlazeCPU *cpu; CPUMBState *env; static int tcg_initialized = 0; int i; - env = g_malloc0(sizeof(CPUMBState)); + cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); + env = &cpu->env; - cpu_exec_init(env); - cpu_state_reset(env); qemu_init_vcpu(env); - set_float_rounding_mode(float_round_nearest_even, &env->fp_status); if (tcg_initialized) return env; @@ -1941,54 +1940,7 @@ CPUMBState *cpu_mb_init (const char *cpu_model) void cpu_state_reset(CPUMBState *env) { - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); - log_cpu_state(env, 0); - } - - memset(env, 0, offsetof(CPUMBState, breakpoints)); - tlb_flush(env, 1); - - /* Disable stack protector. */ - env->shr = ~0; - - env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ - | PVR0_USE_BARREL_MASK \ - | PVR0_USE_DIV_MASK \ - | PVR0_USE_HW_MUL_MASK \ - | PVR0_USE_EXC_MASK \ - | PVR0_USE_ICACHE_MASK \ - | PVR0_USE_DCACHE_MASK \ - | PVR0_USE_MMU \ - | (0xb << 8); - env->pvr.regs[2] = PVR2_D_OPB_MASK \ - | PVR2_D_LMB_MASK \ - | PVR2_I_OPB_MASK \ - | PVR2_I_LMB_MASK \ - | PVR2_USE_MSR_INSTR \ - | PVR2_USE_PCMP_INSTR \ - | PVR2_USE_BARREL_MASK \ - | PVR2_USE_DIV_MASK \ - | PVR2_USE_HW_MUL_MASK \ - | PVR2_USE_MUL64_MASK \ - | PVR2_USE_FPU_MASK \ - | PVR2_USE_FPU2_MASK \ - | PVR2_FPU_EXC_MASK \ - | 0; - env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ - env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); - -#if defined(CONFIG_USER_ONLY) - /* start in user mode with interrupts enabled. */ - env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; - env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ -#else - env->sregs[SR_MSR] = 0; - mmu_init(&env->mmu); - env->mmu.c_mmu = 3; - env->mmu.c_mmu_tlb_access = 3; - env->mmu.c_mmu_zones = 16; -#endif + cpu_reset(ENV_GET_CPU(env)); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos) -- 1.7.7
