On Fri, 16 Feb 2024, Richard Henderson wrote:
> Benchmark each acceleration function vs an aligned buffer of zeros.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> +
> +static void test(const void *opaque)
> +{
> + size_t len = 64 * KiB;
This exceeds L1 cache capacity, so the performance ceiling of L2 cache
throughput is easier to hit with a suboptimal implementation. It also
seems to vastly exceed typical buffer sizes in Qemu.
When preparing the patch we mostly tested at 8 KiB. The size decides
whether the branch exiting the loop becomes perfectly predictable in
the microbenchmark, e.g. at 128 bytes per iteration it exits on the
63'rd iteration, which Intel predictors cannot track, so we get
one mispredict per call.
(so perhaps smaller sizes like 2 or 4 KiB are better)
Alexander
