On Thu, Jan 25, 2024 at 04:53:19PM -0300, Daniel Henrique Barboza wrote:
> From: Andrew Jones <ajo...@ventanamicro.com>
>
> Named features are extensions which don't make sense for users to
> control and are therefore not exposed on the command line. However,
> svade is an extension which makes sense for users to control, so treat
> it like a "normal" extension. The default is false, since QEMU has
> always implemented hardware A/D PTE bit updating, so users must opt into
> svade (or get it from a CPU type which enables it by default).
>
> Signed-off-by: Andrew Jones <ajo...@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> ---
> target/riscv/cpu.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a56c2ff91d..4ddde25412 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1421,6 +1421,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>
> MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
> MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
> + MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
I forgot that the 'max' cpu type will ignore this off by default setting
and enable svade by default. I'll send a v2 of this series where I ensure
svade for 'max' also defaults false.
Thanks,
drew
> MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
> @@ -1528,7 +1529,6 @@ const RISCVCPUMultiExtConfig
> riscv_cpu_experimental_exts[] = {
> * and priv_ver like regular extensions.
> */
> const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
> - MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
> MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
>
> /*
> @@ -2175,8 +2175,6 @@ static RISCVCPUProfile RVA22U64 = {
> * Other named features that we already implement: Sstvecd, Sstvala,
> * Sscounterenw
> *
> - * Named features that we need to enable: svade
> - *
> * The remaining features/extensions comes from RVA22U64.
> */
> static RISCVCPUProfile RVA22S64 = {
> @@ -2188,11 +2186,11 @@ static RISCVCPUProfile RVA22S64 = {
> .ext_offsets = {
> /* rva22s64 exts */
> CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
> - CPU_CFG_OFFSET(ext_svinval),
> + CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
>
> /* rva22s64 named features */
> CPU_CFG_OFFSET(ext_sstvecd), CPU_CFG_OFFSET(ext_sstvala),
> - CPU_CFG_OFFSET(ext_sscounterenw), CPU_CFG_OFFSET(ext_svade),
> + CPU_CFG_OFFSET(ext_sscounterenw),
>
> RISCV_PROFILE_EXT_LIST_END
> }
> --
> 2.43.0
>
