On Wed, Jan 10, 2024 at 8:27 PM Conor Dooley <co...@kernel.org> wrote: > > From: Conor Dooley <conor.doo...@microchip.com> > > Making it a series to keep the standalone change to riscv_isa_string() > that Drew reported separate. > > Changes in v3: > - g_free() isa_extensions too > - use misa_mxl_max rather than the compile target for the base isa > - add a new patch changing riscv_isa_string() to do the same > - drop a null check that cannot be null > - rebased on top of Alistair's next branch
Do you mind rebasing on https://github.com/alistair23/qemu/tree/riscv-to-apply.next again? There was a big re-org recently so lots of rebasing is required Alistair > > Changes in v2: > - use g_strdup() for multiletter extension string copying > - wrap stuff in #ifndef to prevent breaking the user mode build > - rename riscv_isa_set_props() -> riscv_isa_write_fdt() > > CC: Alistair Francis <alistair.fran...@wdc.com> > CC: Bin Meng <bin.m...@windriver.com> > CC: Palmer Dabbelt <pal...@dabbelt.com> > CC: Weiwei Li <liwei1...@gmail.com> > CC: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > CC: Andrew Jones <ajo...@ventanamicro.com> > CC: Liu Zhiwei <zhiwei_...@linux.alibaba.com> > CC: qemu-ri...@nongnu.org > CC: qemu-devel@nongnu.org > > Conor Dooley (2): > target/riscv: use misa_mxl_max to populate isa string rather than > TARGET_LONG_BITS > target/riscv: support new isa extension detection devicetree > properties > > hw/riscv/sifive_u.c | 7 ++---- > hw/riscv/spike.c | 6 ++--- > hw/riscv/virt.c | 6 ++--- > target/riscv/cpu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++- > target/riscv/cpu.h | 1 + > 5 files changed, 63 insertions(+), 14 deletions(-) > > -- > 2.39.2 > >
