On Tue, Jan 9, 2024 at 2:19 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> A bare bones 32 bit RVI CPU, rv32i, will make users lives easier when a
> full customized 32 bit CPU is desired, and users won't need to disable
> defaults by hand as they would with the rv32 CPU. [1] has an example of
> a situation that would be avoided with rv32i.
>
> In fact, add bare bones CPUs for RVE as well. Trying to use RVE in QEMU
> requires one to disable every single default extension, including RVI,
> and then add the desirable extension set. Adding rv32e/rv64e makes it
> more pleasant to use embedded CPUs in QEMU.
>
> [1]
> https://lore.kernel.org/qemu-riscv/258be47f-97be-4308-bed5-dc34ef7ff954@Spark/
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 3 +++
> target/riscv/cpu.c | 21 +++++++++++++++++++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 9219c2fcc3..3670cfe6d9 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -34,7 +34,10 @@
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
> +#define TYPE_RISCV_CPU_RV32I RISCV_CPU_TYPE_NAME("rv32i")
> +#define TYPE_RISCV_CPU_RV32E RISCV_CPU_TYPE_NAME("rv32e")
> #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
> +#define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e")
> #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
> #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1202ec3e57..b9f10b773b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -576,6 +576,12 @@ static void rv64i_bare_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> riscv_cpu_set_misa(env, MXL_RV64, RVI);
> }
> +
> +static void rv64e_bare_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + riscv_cpu_set_misa(env, MXL_RV64, RVE);
> +}
> #else
> static void rv32_base_cpu_init(Object *obj)
> {
> @@ -657,6 +663,18 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> cpu->cfg.ext_zicsr = true;
> cpu->cfg.pmp = true;
> }
> +
> +static void rv32i_bare_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + riscv_cpu_set_misa(env, MXL_RV32, RVI);
> +}
> +
> +static void rv32e_bare_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + riscv_cpu_set_misa(env, MXL_RV32, RVE);
> +}
> #endif
>
> static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
> @@ -1948,6 +1966,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34,
> rv32_imafcu_nommu_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
> + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, rv32i_bare_cpu_init),
> + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, rv32e_bare_cpu_init),
> #elif defined(TARGET_RISCV64)
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
> @@ -1957,6 +1977,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
> + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, rv64e_bare_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init),
> #endif
> --
> 2.43.0
>
>
