This patch adds a new device STM32L4x5 GPIO device and is part
of a series implementing the STM32L4x5 with a few peripherals.
This is RFC as the tests need to be corrected and completed.
The way the short-circuits are handled in the code currently :
(0) The model is simplified (it detects pins driven internally and
externally, not actual short-circuits)
(1) It reacts by ignoring external driving and writes
a `qemu_log_mask` about it
(2) The model is tested by using a fake register
`GPIO_DISCONNECTED_PINS` which is quite practical.
However the tests could disconnect pins and check if a pin is
disconnected in other ways (like setting all pins in push-pull
output to disconnect them), should I unmap this attribute?
Some context and more details for (0)
This code uses a simplified model. Instead of checking for
short-circuits each time the driving (internal and external) changes,
some configurations aren't allowed :
- push-pull with external driving
- open-drain with pin set high
Concretely, the pins configured as output can't be set externally
when in push-pull mode, or set high when in open-drain mode.
Conversely, when input/output mode or push-pull/open-drain mode
is changed, the problematic pins driven externally are "disconnected"
and the external value isn't considered anymore.
I saw sifive_gpio.c uses a similar model :
```
/* Pin both driven externally and internally */
if (output_en && in_mask) {
qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i);
}
```
But nrf51_gpio.c actually checks for short-circuits :
```
if (connected_out && connected_in && out != in) {
/* Pin both driven externally and internally */
qemu_log_mask(LOG_GUEST_ERROR,
"GPIO pin %zu short circuited\n", i);
}
```
Based-on: 20240109194438.70934-1-ines.var...@telecom-paris.fr
([PATCH v4 0/3] Add device STM32L4x5 SYSCFG)
Signed-off-by: Arnaud Minier <arnaud.min...@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.var...@telecom-paris.fr>
Inès Varhol (3):
hw/gpio: Implement STM32L4x5 GPIO
hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
tests/qtest: Add STM32L4x5 GPIO QTest testcase
docs/system/arm/b-l475e-iot01a.rst | 2 +-
hw/arm/Kconfig | 3 +-
hw/arm/stm32l4x5_soc.c | 62 +++-
hw/gpio/Kconfig | 3 +
hw/gpio/meson.build | 1 +
hw/gpio/stm32l4x5_gpio.c | 520 +++++++++++++++++++++++++++++
hw/gpio/trace-events | 6 +
include/hw/arm/stm32l4x5_soc.h | 9 +
include/hw/gpio/stm32l4x5_gpio.h | 79 +++++
tests/qtest/meson.build | 3 +-
tests/qtest/stm32l4x5_gpio-test.c | 319 ++++++++++++++++++
11 files changed, 991 insertions(+), 16 deletions(-)
create mode 100644 hw/gpio/stm32l4x5_gpio.c
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
--
2.43.0
