On Thu, 11 Jan 2024 at 11:05, Peter Maydell <peter.mayd...@linaro.org> wrote: > > Mostly my FEAT_NV/NV2 stuff, but some other smaller series too. > > -- PMM > > The following changes since commit 9468484fe904ab4691de6d9c34616667f377ceac: > > Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into > staging (2024-01-09 10:32:23 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20240111 > > for you to fetch changes up to e2862554c257e908a3833265e38365e794abd362: > > target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs (2024-01-09 > 14:44:45 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * Emulate FEAT_NV, FEAT_NV2 > * add cache controller for Freescale i.MX6 > * Add minimal support for the B-L475E-IOT01A board > * Allow SoC models to configure M-profile CPUs with correct number > of NVIC priority bits > * Add missing QOM parent for v7-M SoCs > * Set CTR_EL0.{IDC,DIC} for the 'max' CPU > * hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers > > ----------------------------------------------------------------
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0 for any user-visible changes. -- PMM
