On 1/7/24 04:43, Paolo Bonzini wrote:
On Sat, Oct 28, 2023 at 9:45 PM Richard Henderson <richard.hender...@linaro.org> wrote:Expose a pair of comparison operators that map to the "test" comparison that is available on many architectures. Changes for v2: * Add TCGCond to tcg_target_const_match. This fixes a long-standing issue with ppc and s390x backends, in that CMPI for signed comparisons has signed immediate and CMPLI for unsigned comparisons has unsigned immediate. But now allows different immediates for the TST comparisons. * tcg/i386: Generate TEST x,x for power-of-two in {7,15,31,63}. * tcg/i386: Generate BT n,x for other power-of-two. * tcg/ppc: tcg_target_const_match improvements * tcg/s390x: tcg_target_const_match improvements * target/m68k: Use TST{EQ,NE} for gen_fcc_cond.I updated the MIPS backend (untested though) and pushed the result to branch i386 of https://gitlab.com/bonzini/qemu/.
Thanks.
However I was thinking: a lot of RISC targets simply do AND/ANDI followed by the sequence used for TCG_COND_NE. Would it make sense to have a TCG_TARGET_SUPPORTS_TST bit and, if absent, lower TSTEQ/TSTNE to AND+EQ/NE directly in the optimizer?
Probably best, yes.
And for brcond2/setcond2, always using AND/AND/OR may work just as well as any backend-specific trick, and will give more freedom to the register allocator.
test a,b testeq c,e for Arm32. So I'll leave it to the backends. r~
