On Wed, 3 Jan 2024 at 15:53, Samuel Tardieu <s...@rfc1149.net> wrote: > > Cortex-M NVIC can have a different number of priority bits. > Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based > on ARMv7m and up must use 3 or more bits. > > This adds a "num-prio-bits" property which will get sensible default > values if unset (2 or 8 depending on the device). Unless a SOC > specifies the number of bits to use, the previous behavior is > maintained for backward compatibility. > > Signed-off-by: Samuel Tardieu <s...@rfc1149.net> > Suggested-by: Anton Kochkov <anton.koch...@proton.me> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122 > ---
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
