Having moved the reset code for some CPUs to class_init, we can drop
some of the cases in the switch.
Signed-off-by: Andreas Färber <afaer...@suse.de>
Cc: Peter Maydell <peter.mayd...@linaro.org>
---
target-arm/cpu.h | 2 --
target-arm/helper.c | 5 -----
2 files changed, 0 insertions(+), 7 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index d14fb01..48d42b7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -427,8 +427,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define ARM_CPUID_CORTEXA8 0x410fc080
#define ARM_CPUID_CORTEXA9 0x410fc090
#define ARM_CPUID_CORTEXA15 0x412fc0f1
-#define ARM_CPUID_CORTEXM3 0x410fc231
-#define ARM_CPUID_ANY 0xffffffff
#if defined(CONFIG_USER_ONLY)
#define TARGET_PAGE_BITS 12
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 0dd6065..59a9812 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -136,10 +136,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
env->cp15.c1_sys = 0x00c50078;
break;
- case ARM_CPUID_CORTEXM3:
- break;
- case ARM_CPUID_ANY: /* For userspace emulation. */
- break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
env->cp15.c0_cachetype = 0x5109149;
@@ -172,7 +168,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c1_sys = 0x00000070;
break;
default:
- cpu_abort(env, "Bad CPU ID: %x\n", id);
break;
}
}
--
1.7.7
