On Tue Nov 28, 2023 at 3:13 AM AEST, Chalapathi V wrote:
> A POWER10 chip is divided into logical pieces called chiplets. Chiplets
> are broadly divided into "core chiplets" (with the processor cores) and
> "nest chiplets" (with everything else). Each chiplet has an attachment
> to the pervasive bus (PIB) and with chiplet-specific registers. All nest
> chiplets have a common basic set of registers and This model will provide
> the registers functionality for common registers of nest chiplet (Pervasive
> Chiplet, PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
>
> This commit implement the read/write functions of chiplet control registers.
>
> Signed-off-by: Chalapathi V <chalapath...@linux.ibm.com>
> ---
> include/hw/ppc/pnv_nest_pervasive.h | 36 +++++
> include/hw/ppc/pnv_xscom.h | 3 +
> hw/ppc/pnv_nest_pervasive.c | 219 ++++++++++++++++++++++++++++
> hw/ppc/meson.build | 1 +
> 4 files changed, 259 insertions(+)
> create mode 100644 include/hw/ppc/pnv_nest_pervasive.h
> create mode 100644 hw/ppc/pnv_nest_pervasive.c
>
> diff --git a/include/hw/ppc/pnv_nest_pervasive.h
> b/include/hw/ppc/pnv_nest_pervasive.h
> new file mode 100644
> index 0000000000..9f11531f52
> --- /dev/null
> +++ b/include/hw/ppc/pnv_nest_pervasive.h
> @@ -0,0 +1,36 @@
> +/*
> + * QEMU PowerPC nest pervasive common chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
Shouldn't need this line with the SPDX tag I think? There are a copule
of dozen files already in the tree that do have both, but hundreds that
only have the tag.
> + */
> +
> +#ifndef PPC_PNV_NEST_PERVASIVE_H
> +#define PPC_PNV_NEST_PERVASIVE_H
> +
> +#define TYPE_PNV_NEST_PERVASIVE "pnv-nest-chiplet-pervasive"
> +#define PNV_NEST_PERVASIVE(obj) OBJECT_CHECK(PnvNestChipletPervasive, (obj),
> TYPE_PNV_NEST_PERVASIVE)
_NEXT_CHIPLET_PERVASIVE?
> +
> +typedef struct PnvPervasiveCtrlRegs {
> +#define CPLT_CTRL_SIZE 6
> + uint64_t cplt_ctrl[CPLT_CTRL_SIZE];
> + uint64_t cplt_cfg0;
> + uint64_t cplt_cfg1;
> + uint64_t cplt_stat0;
> + uint64_t cplt_mask0;
> + uint64_t ctrl_protect_mode;
> + uint64_t ctrl_atomic_lock;
> +} PnvPervasiveCtrlRegs;
> +
> +typedef struct PnvNestChipletPervasive {
> + DeviceState parent;
> + char *parent_obj_name;
> + MemoryRegion xscom_ctrl_regs;
> + PnvPervasiveCtrlRegs control_regs;
> +} PnvNestChipletPervasive;
The file name doesn't quite match the type name, but that's probably
okay. This could be a good place for other misc pervasive helpers,
so keeping the name more general is fine.
> +
> +#endif /*PPC_PNV_NEST_PERVASIVE_H */
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index f5becbab41..3e15706dec 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -170,6 +170,9 @@ struct PnvXScomInterfaceClass {
> #define PNV10_XSCOM_XIVE2_BASE 0x2010800
> #define PNV10_XSCOM_XIVE2_SIZE 0x400
>
> +#define PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE 0x3000000
> +#define PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE 0x400
> +
> #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
> #define PNV10_XSCOM_PEC_NEST_SIZE 0x100
>
> diff --git a/hw/ppc/pnv_nest_pervasive.c b/hw/ppc/pnv_nest_pervasive.c
> new file mode 100644
> index 0000000000..0575f87e8f
> --- /dev/null
> +++ b/hw/ppc/pnv_nest_pervasive.c
> @@ -0,0 +1,219 @@
> +/*
> + * QEMU PowerPC nest pervasive common chiplet model
> + *
> + * Copyright (c) 2023, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This code is licensed under the GPL version 2 or later. See the
> + * COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/ppc/pnv.h"
> +#include "hw/ppc/pnv_xscom.h"
> +#include "hw/ppc/pnv_nest_pervasive.h"
> +
> +/*
> + * Status, configuration, and control units in POWER chips is provided
> + * by the pervasive subsystem, which connects registers to the SCOM bus,
> + * which can be programmed by processor cores, other units on the chip,
> + * BMCs, or other POWER chips.
> + *
> + * A POWER10 chip is divided into logical pieces called chiplets. Chiplets
> + * are broadly divided into "core chiplets" (with the processor cores) and
> + * "nest chiplets" (with everything else). Each chiplet has an attachment
> + * to the nest_pervasiveasive bus (PIB) and with chiplet-specific registers.
> + * All nest chiplets have a common basic set of registers.
> + *
> + * This model will provide the registers fuctionality for common registers of
> + * nest unit (PB Chiplet, PCI Chiplets, MC Chiplet, PAU Chiplets)
> + *
> + * Currently this model provide the read/write fuctionality of chiplet
> control
> + * scom registers.
> + */
> +
> +#define CPLT_CONF0 0x08
> +#define CPLT_CONF0_OR 0x18
> +#define CPLT_CONF0_CLEAR 0x28
> +#define CPLT_CONF1 0x09
> +#define CPLT_CONF1_OR 0x19
> +#define CPLT_CONF1_CLEAR 0x29
> +#define CPLT_STAT0 0x100
> +#define CPLT_MASK0 0x101
> +#define CPLT_PROTECT_MODE 0x3FE
> +#define CPLT_ATOMIC_CLOCK 0x3FF
> +
> +static uint64_t pnv_chiplet_ctrl_read(void *opaque, hwaddr addr, unsigned
> size)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(opaque);
> + int reg = addr >> 3;
> + uint64_t val = ~0ull;
> +
> + /* CPLT_CTRL0 to CPLT_CTRL5 */
> + for (int i = 0; i < CPLT_CTRL_SIZE; i++) {
> + if (reg == i) {
> + return nest_pervasive->control_regs.cplt_ctrl[i];
> + } else if ((reg == (i + 0x10)) || (reg == (i + 0x20))) {
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register,
> ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + return val;
> + }
> + }
> +
> + switch (reg) {
> + case CPLT_CONF0:
> + val = nest_pervasive->control_regs.cplt_cfg0;
> + break;
> + case CPLT_CONF0_OR:
> + case CPLT_CONF0_CLEAR:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + break;
> + case CPLT_CONF1:
> + val = nest_pervasive->control_regs.cplt_cfg1;
> + break;
> + case CPLT_CONF1_OR:
> + case CPLT_CONF1_CLEAR:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring "
> + "xscom read at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + break;
> + case CPLT_STAT0:
> + val = nest_pervasive->control_regs.cplt_stat0;
> + break;
> + case CPLT_MASK0:
> + val = nest_pervasive->control_regs.cplt_mask0;
> + break;
> + case CPLT_PROTECT_MODE:
> + val = nest_pervasive->control_regs.ctrl_protect_mode;
> + break;
> + case CPLT_ATOMIC_CLOCK:
> + val = nest_pervasive->control_regs.ctrl_atomic_lock;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
> + "read at 0x%" PRIx64 "\n", __func__, (unsigned long)reg);
> + }
> + return val;
> +}
> +
> +static void pnv_chiplet_ctrl_write(void *opaque, hwaddr addr,
> + uint64_t val, unsigned size)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(opaque);
> + int reg = addr >> 3;
> +
> + /* CPLT_CTRL0 to CPLT_CTRL5 */
> + for (int i = 0; i < CPLT_CTRL_SIZE; i++) {
> + if (reg == i) {
> + nest_pervasive->control_regs.cplt_ctrl[i] = val;
> + return;
> + } else if (reg == (i + 0x10)) {
> + nest_pervasive->control_regs.cplt_ctrl[i] |= val;
> + return;
> + } else if (reg == (i + 0x20)) {
> + nest_pervasive->control_regs.cplt_ctrl[i] &= ~val;
> + return;
> + }
> + }
> +
> + switch (reg) {
> + case CPLT_CONF0:
> + nest_pervasive->control_regs.cplt_cfg0 = val;
> + break;
> + case CPLT_CONF0_OR:
> + nest_pervasive->control_regs.cplt_cfg0 |= val;
> + break;
> + case CPLT_CONF0_CLEAR:
> + nest_pervasive->control_regs.cplt_cfg0 &= ~val;
> + break;
> + case CPLT_CONF1:
> + nest_pervasive->control_regs.cplt_cfg1 = val;
> + break;
> + case CPLT_CONF1_OR:
> + nest_pervasive->control_regs.cplt_cfg1 |= val;
> + break;
> + case CPLT_CONF1_CLEAR:
> + nest_pervasive->control_regs.cplt_cfg1 &= ~val;
> + break;
> + case CPLT_STAT0:
> + nest_pervasive->control_regs.cplt_stat0 = val;
> + break;
> + case CPLT_MASK0:
> + nest_pervasive->control_regs.cplt_mask0 = val;
> + break;
> + case CPLT_PROTECT_MODE:
> + nest_pervasive->control_regs.ctrl_protect_mode = val;
> + break;
> + case CPLT_ATOMIC_CLOCK:
> + nest_pervasive->control_regs.ctrl_atomic_lock = val;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom "
> + "write at 0x%" PRIx64 "\n",
> + __func__, (unsigned long)reg);
> + }
> +}
> +
> +static const MemoryRegionOps pnv_nest_pervasive_control_xscom_ops = {
> + .read = pnv_chiplet_ctrl_read,
> + .write = pnv_chiplet_ctrl_write,
> + .valid.min_access_size = 8,
> + .valid.max_access_size = 8,
> + .impl.min_access_size = 8,
> + .impl.max_access_size = 8,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static void pnv_nest_pervasive_realize(DeviceState *dev, Error **errp)
> +{
> + PnvNestChipletPervasive *nest_pervasive = PNV_NEST_PERVASIVE(dev);
> + g_autofree char *region_name = NULL;
> + region_name = g_strdup_printf("xscom-%s-control-regs",
> + nest_pervasive->parent_obj_name);
Should it be just control, or pervasive-control? Nest chiplets will
have control for other functions.
Those are all minor nits though. Generally looks good.
Reviewed-by: Nicholas Piggin <npig...@gmail.com>
> +
> + /* Chiplet control scoms */
> + pnv_xscom_region_init(&nest_pervasive->xscom_ctrl_regs,
> + OBJECT(nest_pervasive),
> + &pnv_nest_pervasive_control_xscom_ops,
> + nest_pervasive, region_name,
> + PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE);
> +}
> +
> +static Property pnv_nest_pervasive_properties[] = {
> + DEFINE_PROP_STRING("parent-obj-name", PnvNestChipletPervasive,
> + parent_obj_name),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void pnv_nest_pervasive_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "PowerNV nest_pervasive chiplet";
> + dc->realize = pnv_nest_pervasive_realize;
> + device_class_set_props(dc, pnv_nest_pervasive_properties);
> +}
> +
> +static const TypeInfo pnv_nest_pervasive_info = {
> + .name = TYPE_PNV_NEST_PERVASIVE,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvNestChipletPervasive),
> + .class_init = pnv_nest_pervasive_class_init,
> + .interfaces = (InterfaceInfo[]) {
> + { TYPE_PNV_XSCOM_INTERFACE },
> + { }
> + }
> +};
> +
> +static void pnv_nest_pervasive_register_types(void)
> +{
> + type_register_static(&pnv_nest_pervasive_info);
> +}
> +
> +type_init(pnv_nest_pervasive_register_types);
> diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
> index ea44856d43..d6f6f94fcc 100644
> --- a/hw/ppc/meson.build
> +++ b/hw/ppc/meson.build
> @@ -51,6 +51,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
> 'pnv_bmc.c',
> 'pnv_homer.c',
> 'pnv_pnor.c',
> + 'pnv_nest_pervasive.c',
> ))
> # PowerPC 4xx boards
> ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
