On Thu, Nov 23, 2023 at 04:15:32PM -0300, Daniel Henrique Barboza wrote:
> Add a new profile CPU 'rva22s64' to work as an alias of
>
> -cpu rv64i,rva22s64
>
> Like the existing rva22u64 CPU already does with the RVA22U64 profile.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 8 ++++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 12fe78fc52..9219c2fcc3 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -36,6 +36,7 @@
> #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
> #define TYPE_RISCV_CPU_RV64I RISCV_CPU_TYPE_NAME("rv64i")
> #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
> +#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d00548d164..f6d1d4c7a6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1631,6 +1631,13 @@ static void rva22u64_profile_cpu_init(Object *obj)
>
> RVA22U64.enabled = true;
> }
> +
> +static void rva22s64_profile_cpu_init(Object *obj)
> +{
> + rv64i_bare_cpu_init(obj);
> +
> + RVA22S64.enabled = true;
> +}
> #endif
>
> static const gchar *riscv_gdb_arch_name(CPUState *cs)
> @@ -1975,6 +1982,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init),
> + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init),
> #endif
> };
>
> --
> 2.41.0
>
Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
