Set mc->valid_cpu_types so that the user specified CPU type can
be validated in machine_run_board_init(). We needn't to do it by
ourselves.
Signed-off-by: Gavin Shan <gs...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
---
hw/arm/bananapi_m2u.c | 12 ++++++------
hw/arm/cubieboard.c | 12 ++++++------
hw/arm/mps2-tz.c | 20 ++++++++++++++------
hw/arm/mps2.c | 25 +++++++++++++++++++------
hw/arm/msf2-som.c | 12 ++++++------
hw/arm/musca.c | 13 ++++++-------
hw/arm/npcm7xx_boards.c | 13 ++++++-------
hw/arm/orangepi.c | 12 ++++++------
8 files changed, 69 insertions(+), 50 deletions(-)
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index 8f24b18d8c..5eed11fe03 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -30,6 +30,11 @@
static struct arm_boot_info bpim2u_binfo;
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a7"),
+ NULL
+};
+
/*
* R40 can boot from mmc0 and mmc2, and bpim2u has two mmc interface, one is
* connected to sdcard and another mount an emmc media.
@@ -71,12 +76,6 @@ static void bpim2u_init(MachineState *machine)
exit(1);
}
- /* Only allow Cortex-A7 for this board */
- if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
- error_report("This board can only be used with cortex-a7 CPU");
- exit(1);
- }
-
r40 = AW_R40(object_new(TYPE_AW_R40));
object_property_add_child(OBJECT(machine), "soc", OBJECT(r40));
object_unref(OBJECT(r40));
@@ -139,6 +138,7 @@ static void bpim2u_machine_init(MachineClass *mc)
mc->max_cpus = AW_R40_NUM_CPUS;
mc->default_cpus = AW_R40_NUM_CPUS;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
+ mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_ram_id = "bpim2u.ram";
}
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 29146f5018..7d9bb6c837 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -29,6 +29,11 @@ static struct arm_boot_info cubieboard_binfo = {
.board_id = 0x1008,
};
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a8"),
+ NULL
+};
+
static void cubieboard_init(MachineState *machine)
{
AwA10State *a10;
@@ -52,12 +57,6 @@ static void cubieboard_init(MachineState *machine)
exit(1);
}
- /* Only allow Cortex-A8 for this board */
- if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a8")) != 0) {
- error_report("This board can only be used with cortex-a8 CPU");
- exit(1);
- }
-
a10 = AW_A10(object_new(TYPE_AW_A10));
object_property_add_child(OBJECT(machine), "soc", OBJECT(a10));
object_unref(OBJECT(a10));
@@ -116,6 +115,7 @@ static void cubieboard_machine_init(MachineClass *mc)
{
mc->desc = "cubietech cubieboard (Cortex-A8)";
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
+ mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->init = cubieboard_init;
mc->block_default_type = IF_IDE;
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 668db5ed61..1c88e76a22 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -191,6 +191,16 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState,
MPS2TZMachineClass, MPS2TZ_MACHINE)
/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
#define MPU_REGION_DEFAULT UINT32_MAX
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m33"),
+ NULL
+};
+
+static const char * const mps3tz_an547_valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m55"),
+ NULL
+};
+
static const uint32_t an505_oscclk[] = {
40000000,
24580000,
@@ -813,12 +823,6 @@ static void mps2tz_common_init(MachineState *machine)
int num_ppcs;
int i;
- if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
- error_report("This board can only be used with CPU %s",
- mc->default_cpu_type);
- exit(1);
- }
-
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
error_report("Invalid RAM size, should be %s", sz);
@@ -1325,6 +1329,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void
*data)
mc->max_cpus = mc->default_cpus;
mmc->fpga_type = FPGA_AN505;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
+ mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045050;
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
mmc->apb_periph_frq = mmc->sysclk_frq;
@@ -1354,6 +1359,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void
*data)
mc->max_cpus = mc->default_cpus;
mmc->fpga_type = FPGA_AN521;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
+ mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045210;
mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */
mmc->apb_periph_frq = mmc->sysclk_frq;
@@ -1383,6 +1389,7 @@ static void mps3tz_an524_class_init(ObjectClass *oc, void
*data)
mc->max_cpus = mc->default_cpus;
mmc->fpga_type = FPGA_AN524;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
+ mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045240;
mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
mmc->apb_periph_frq = mmc->sysclk_frq;
@@ -1417,6 +1424,7 @@ static void mps3tz_an547_class_init(ObjectClass *oc, void
*data)
mc->max_cpus = mc->default_cpus;
mmc->fpga_type = FPGA_AN547;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m55");
+ mc->valid_cpu_types = mps3tz_an547_valid_cpu_types;
mmc->scc_id = 0x41055470;
mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */
mmc->apb_periph_frq = 25 * 1000 * 1000; /* 25MHz */
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 292a180ad2..3baff18571 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -111,6 +111,21 @@ OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass,
MPS2_MACHINE)
*/
#define REFCLK_FRQ (1 * 1000 * 1000)
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m3"),
+ NULL
+};
+
+static const char * const mps2_an386_valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"),
+ NULL
+};
+
+static const char * const mps2_an500_valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m7"),
+ NULL
+};
+
/* Initialize the auxiliary RAM region @mr and map it into
* the memory map at @base.
*/
@@ -142,12 +157,6 @@ static void mps2_common_init(MachineState *machine)
QList *oscclk;
int i;
- if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
- error_report("This board can only be used with CPU %s",
- mc->default_cpu_type);
- exit(1);
- }
-
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
error_report("Invalid RAM size, should be %s", sz);
@@ -488,6 +497,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void
*data)
mc->desc = "ARM MPS2 with AN385 FPGA image for Cortex-M3";
mmc->fpga_type = FPGA_AN385;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
+ mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41043850;
mmc->psram_base = 0x21000000;
mmc->ethernet_base = 0x40200000;
@@ -502,6 +512,7 @@ static void mps2_an386_class_init(ObjectClass *oc, void
*data)
mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
mmc->fpga_type = FPGA_AN386;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+ mc->valid_cpu_types = mps2_an386_valid_cpu_types;
mmc->scc_id = 0x41043860;
mmc->psram_base = 0x21000000;
mmc->ethernet_base = 0x40200000;
@@ -516,6 +527,7 @@ static void mps2_an500_class_init(ObjectClass *oc, void
*data)
mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
mmc->fpga_type = FPGA_AN500;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
+ mc->valid_cpu_types = mps2_an500_valid_cpu_types;
mmc->scc_id = 0x41045000;
mmc->psram_base = 0x60000000;
mmc->ethernet_base = 0xa0000000;
@@ -530,6 +542,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void
*data)
mc->desc = "ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3";
mmc->fpga_type = FPGA_AN511;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
+ mc->valid_cpu_types = valid_cpu_types;
mmc->scc_id = 0x41045110;
mmc->psram_base = 0x21000000;
mmc->ethernet_base = 0x40200000;
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 7b3106c790..470951a006 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -42,6 +42,11 @@
#define M2S010_ENVM_SIZE (256 * KiB)
#define M2S010_ESRAM_SIZE (64 * KiB)
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m3"),
+ NULL
+};
+
static void emcraft_sf2_s2s010_init(MachineState *machine)
{
DeviceState *dev;
@@ -55,12 +60,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
MemoryRegion *ddr = g_new(MemoryRegion, 1);
Clock *m3clk;
- if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
- error_report("This board can only be used with CPU %s",
- mc->default_cpu_type);
- exit(1);
- }
-
memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
&error_fatal);
memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
@@ -109,6 +108,7 @@ static void emcraft_sf2_machine_init(MachineClass *mc)
mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)";
mc->init = emcraft_sf2_s2s010_init;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
+ mc->valid_cpu_types = valid_cpu_types;
}
DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 6eeee57c9d..9bd78fd531 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -102,6 +102,11 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass,
MUSCA_MACHINE)
/* Slow 32Khz S32KCLK frequency in Hz */
#define S32KCLK_FRQ (32 * 1000)
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m33"),
+ NULL
+};
+
static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
{
/* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
@@ -355,7 +360,6 @@ static void musca_init(MachineState *machine)
{
MuscaMachineState *mms = MUSCA_MACHINE(machine);
MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms);
- MachineClass *mc = MACHINE_GET_CLASS(machine);
MemoryRegion *system_memory = get_system_memory();
DeviceState *ssedev;
DeviceState *dev_splitter;
@@ -366,12 +370,6 @@ static void musca_init(MachineState *machine)
assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX);
assert(mmc->num_mpcs <= MUSCA_MPC_MAX);
- if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
- error_report("This board can only be used with CPU %s",
- mc->default_cpu_type);
- exit(1);
- }
-
mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(mms->sysclk, SYSCLK_FRQ);
mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
@@ -609,6 +607,7 @@ static void musca_class_init(ObjectClass *oc, void *data)
mc->min_cpus = mc->default_cpus;
mc->max_cpus = mc->default_cpus;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33");
+ mc->valid_cpu_types = valid_cpu_types;
mc->init = musca_init;
}
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 2aef579aac..ca37c893b4 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -55,6 +55,11 @@
static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a9"),
+ NULL
+};
+
static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
{
const char *bios_name = machine->firmware ?: npcm7xx_default_bootrom;
@@ -121,15 +126,8 @@ static NPCM7xxState *npcm7xx_create_soc(MachineState
*machine,
uint32_t hw_straps)
{
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
- MachineClass *mc = MACHINE_CLASS(nmc);
Object *obj;
- if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
- error_report("This board can only be used with %s",
- mc->default_cpu_type);
- exit(1);
- }
-
obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
&error_abort, NULL);
object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
@@ -469,6 +467,7 @@ static void npcm7xx_machine_class_init(ObjectClass *oc,
void *data)
mc->no_parallel = 1;
mc->default_ram_id = "ram";
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
+ mc->valid_cpu_types = valid_cpu_types;
}
/*
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index f3784d45ca..4e8a43978d 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -29,6 +29,11 @@
static struct arm_boot_info orangepi_binfo;
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a7"),
+ NULL
+};
+
static void orangepi_init(MachineState *machine)
{
AwH3State *h3;
@@ -49,12 +54,6 @@ static void orangepi_init(MachineState *machine)
exit(1);
}
- /* Only allow Cortex-A7 for this board */
- if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) != 0) {
- error_report("This board can only be used with cortex-a7 CPU");
- exit(1);
- }
-
h3 = AW_H3(object_new(TYPE_AW_H3));
object_property_add_child(OBJECT(machine), "soc", OBJECT(h3));
object_unref(OBJECT(h3));
@@ -119,6 +118,7 @@ static void orangepi_machine_init(MachineClass *mc)
mc->max_cpus = AW_H3_NUM_CPUS;
mc->default_cpus = AW_H3_NUM_CPUS;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
+ mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_ram_id = "orangepi.ram";
}
--
2.41.0
