On Thu, Nov 9, 2023 at 4:20 PM Peter Maydell <peter.mayd...@linaro.org>
wrote:
> AArch64 permits code at EL3 to use the HVC instruction; however the
> exception we take should go to EL3, not down to EL2 (see the pseudocode
> AArch64.CallHypervisor()). Fix the target EL.
>
> Cc: qemu-sta...@nongnu.org
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
>
Reviewed-by: Edgar E. Iglesias <ed...@zeroasic.com>
> ---
> target/arm/tcg/translate-a64.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/tcg/translate-a64.c
> b/target/arm/tcg/translate-a64.c
> index 41484d8ae54..a2e49c39f9f 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -2351,6 +2351,8 @@ static bool trans_SVC(DisasContext *s, arg_i *a)
>
> static bool trans_HVC(DisasContext *s, arg_i *a)
> {
> + int target_el = s->current_el == 3 ? 3 : 2;
> +
> if (s->current_el == 0) {
> unallocated_encoding(s);
> return true;
> @@ -2363,7 +2365,7 @@ static bool trans_HVC(DisasContext *s, arg_i *a)
> gen_helper_pre_hvc(tcg_env);
> /* Architecture requires ss advance before we do the actual work */
> gen_ss_advance(s);
> - gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2);
> + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm),
> target_el);
> return true;
> }
>
> --
> 2.34.1
>
>
>
