On Tue, Nov 07, 2023 at 10:53:40AM +0000, Peter Maydell wrote: > On Tue, 7 Nov 2023 at 03:02, Ethan Chen <etha...@andestech.com> wrote: > > > > On Mon, Nov 06, 2023 at 10:34:41AM +0000, Peter Maydell wrote: > > > What AXI bus signals? You already get address and size in the > > > actual memory transaction, they don't need to go in the MemTxAttrs. > > > > > > > A burst contains multiple continuous read or write operations. In current > > transaction, I can only get the size and address of a single operation. > > IOPMP > > checks not only a single operation but also the burst information. I propose > > to add those signals to MemTxAttrs. > > QEMU doesn't emulate bus transactions at that level -- we have > no concept of burst transactions. You should have the IOMMU > do whatever it would do for a series of simple transactions. >
I propose to use another method like StreamSink in hw/dma/xilinx_axidma.c to let DMA send the signals to IOPMP instead of modifying IOMMU. Thanks, Ethan Chen
