On Thu, Oct 26, 2023 at 6:09 AM Sunil V L <suni...@ventanamicro.com> wrote:
>
> Update the GPEX host bridge properties related to MMIO ranges with
> values set for the virt machine.
>
> Suggested-by: Igor Mammedov <imamm...@redhat.com>
> Signed-off-by: Sunil V L <suni...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> hw/riscv/virt.c | 47 ++++++++++++++++++++++++++++-------------
> include/hw/riscv/virt.h | 1 +
> 2 files changed, 33 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 085654ab2f..e64886a4d8 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -1049,21 +1049,45 @@ static void create_fdt(RISCVVirtState *s, const
> MemMapEntry *memmap)
> }
>
> static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
> - hwaddr ecam_base, hwaddr ecam_size,
> - hwaddr mmio_base, hwaddr mmio_size,
> - hwaddr high_mmio_base,
> - hwaddr high_mmio_size,
> - hwaddr pio_base,
> - DeviceState *irqchip)
> + DeviceState *irqchip,
> + RISCVVirtState *s)
> {
> DeviceState *dev;
> MemoryRegion *ecam_alias, *ecam_reg;
> MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
> + hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
> + hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
> + hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
> + hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
> + hwaddr high_mmio_base = virt_high_pcie_memmap.base;
> + hwaddr high_mmio_size = virt_high_pcie_memmap.size;
> + hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
> + hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
> qemu_irq irq;
> int i;
>
> dev = qdev_new(TYPE_GPEX_HOST);
>
> + /* Set GPEX object properties for the virt machine */
> + object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
> + ecam_base, NULL);
> + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
> + ecam_size, NULL);
> + object_property_set_uint(OBJECT(GPEX_HOST(dev)),
> + PCI_HOST_BELOW_4G_MMIO_BASE,
> + mmio_base, NULL);
> + object_property_set_int(OBJECT(GPEX_HOST(dev)),
> PCI_HOST_BELOW_4G_MMIO_SIZE,
> + mmio_size, NULL);
> + object_property_set_uint(OBJECT(GPEX_HOST(dev)),
> + PCI_HOST_ABOVE_4G_MMIO_BASE,
> + high_mmio_base, NULL);
> + object_property_set_int(OBJECT(GPEX_HOST(dev)),
> PCI_HOST_ABOVE_4G_MMIO_SIZE,
> + high_mmio_size, NULL);
> + object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
> + pio_base, NULL);
> + object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
> + pio_size, NULL);
> +
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> ecam_alias = g_new0(MemoryRegion, 1);
> @@ -1094,6 +1118,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion
> *sys_mem,
> gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
> }
>
> + GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
> return dev;
> }
>
> @@ -1492,15 +1517,7 @@ static void virt_machine_init(MachineState *machine)
> qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
> }
>
> - gpex_pcie_init(system_memory,
> - memmap[VIRT_PCIE_ECAM].base,
> - memmap[VIRT_PCIE_ECAM].size,
> - memmap[VIRT_PCIE_MMIO].base,
> - memmap[VIRT_PCIE_MMIO].size,
> - virt_high_pcie_memmap.base,
> - virt_high_pcie_memmap.size,
> - memmap[VIRT_PCIE_PIO].base,
> - pcie_irqchip);
> + gpex_pcie_init(system_memory, pcie_irqchip, s);
>
> create_platform_bus(s, mmio_irqchip);
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 5b03575ed3..f89790fd58 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -61,6 +61,7 @@ struct RISCVVirtState {
> char *oem_table_id;
> OnOffAuto acpi;
> const MemMapEntry *memmap;
> + struct GPEXHost *gpex_host;
> };
>
> enum {
> --
> 2.39.2
>
>
