Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/sparc/insns.decode | 9 ++++
target/sparc/translate.c | 94 +++++++++++++++++----------------------
2 files changed, 50 insertions(+), 53 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index f197bb0b36..781c3cd7f7 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -327,6 +327,15 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5
BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r
+ FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_r_r
+ FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_r_r
+ FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_r_r
+ FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_r_r
+ FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_r_r
+ FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_r_r
+ FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_r_r
+ FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_r_r
+
FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r
FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r
FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index dee155143c..ff849f33e4 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -77,7 +77,14 @@
#define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; })
#define gen_helper_fexpand ({ g_assert_not_reached(); NULL; })
#define gen_helper_pdist ({ g_assert_not_reached(); NULL; })
-#define gen_helper_fsqrtq ({ g_assert_not_reached(); NULL; })
+#define gen_helper_fcmpeq16 ({ g_assert_not_reached(); NULL; })
+#define gen_helper_fcmpne16 ({ g_assert_not_reached(); NULL; })
+#define gen_helper_fcmple16 ({ g_assert_not_reached(); NULL; })
+#define gen_helper_fcmpgt16 ({ g_assert_not_reached(); NULL; })
+#define gen_helper_fcmpeq32 ({ g_assert_not_reached(); NULL; })
+#define gen_helper_fcmpne32 ({ g_assert_not_reached(); NULL; })
+#define gen_helper_fcmple32 ({ g_assert_not_reached(); NULL; })
+#define gen_helper_fcmpgt32 ({ g_assert_not_reached(); NULL; })
#define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; })
#define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; })
# ifdef CONFIG_USER_ONLY
@@ -5108,6 +5115,37 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32)
TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata)
TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle)
+static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
+ void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
+{
+#ifdef TARGET_SPARC64
+ TCGv_i64 dst, src1, src2;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ dst = gen_dest_gpr(dc, a->rd);
+ src1 = gen_load_fpr_D(dc, a->rs1);
+ src2 = gen_load_fpr_D(dc, a->rs2);
+ func(dst, src1, src2);
+ gen_store_gpr(dc, a->rd, dst);
+ return advance_pc(dc);
+#else
+ g_assert_not_reached();
+#endif
+}
+
+TRANS(FPCMPLE16, VIS1, do_rdd, a, gen_helper_fcmple16)
+TRANS(FPCMPNE16, VIS1, do_rdd, a, gen_helper_fcmpne16)
+TRANS(FPCMPGT16, VIS1, do_rdd, a, gen_helper_fcmpgt16)
+TRANS(FPCMPEQ16, VIS1, do_rdd, a, gen_helper_fcmpeq16)
+
+TRANS(FPCMPLE32, VIS1, do_rdd, a, gen_helper_fcmple32)
+TRANS(FPCMPNE32, VIS1, do_rdd, a, gen_helper_fcmpne32)
+TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32)
+TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32)
+
static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64))
{
@@ -5390,11 +5428,9 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
} else if (xop == 0x36) {
#ifdef TARGET_SPARC64
/* VIS */
- TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
+ TCGv_i64 cpu_src1_64, cpu_dst_64;
TCGv_i32 cpu_dst_32;
- TCGv cpu_dst = tcg_temp_new();
int opf = GET_FIELD_SP(insn, 5, 13);
- int rs1 = GET_FIELD(insn, 13, 17);
int rs2 = GET_FIELD(insn, 27, 31);
int rd = GET_FIELD(insn, 2, 6);
@@ -5470,63 +5506,15 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x03a: /* VIS I fpack32 */
case 0x048: /* VIS I faligndata */
case 0x04c: /* VIS II bshuffle */
- g_assert_not_reached(); /* in decodetree */
case 0x020: /* VIS I fcmple16 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
case 0x022: /* VIS I fcmpne16 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
case 0x024: /* VIS I fcmple32 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
case 0x026: /* VIS I fcmpne32 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
case 0x028: /* VIS I fcmpgt16 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
case 0x02a: /* VIS I fcmpeq16 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
case 0x02c: /* VIS I fcmpgt32 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
case 0x02e: /* VIS I fcmpeq32 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
+ g_assert_not_reached(); /* in decodetree */
case 0x03b: /* VIS I fpack16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
--
2.34.1
