Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/sparc/insns.decode | 3 +++
target/sparc/translate.c | 6 +-----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 1cff18fa1f..1a04a8e229 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -31,6 +31,7 @@ CALL 01 i:s30
&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
+@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
{
[
@@ -165,6 +166,8 @@ ORN 10 ..... 0.0110 ..... . .............
@r_r_ri_cc
XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc
ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc
+MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
+
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
# For v7, the entire simm13 field is present, but masked to 7 bits.
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index c87125a328..be00bd00fc 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4210,6 +4210,7 @@ TRANS(XOR, ALL, do_arith, a, CC_OP_LOGIC, tcg_gen_xor_tl,
tcg_gen_xori_tl)
TRANS(ANDN, ALL, do_arith, a, CC_OP_LOGIC, tcg_gen_andc_tl, NULL)
TRANS(ORN, ALL, do_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL)
TRANS(XORN, ALL, do_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL)
+TRANS(MULX, 64, do_arith, a, 0, tcg_gen_mul_tl, tcg_gen_muli_tl)
static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
{
@@ -4700,11 +4701,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
-#ifdef TARGET_SPARC64
- case 0x9: /* V9 mulx */
- tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
- break;
-#endif
case 0xa: /* umul */
CHECK_IU_FEATURE(dc, MUL);
gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
--
2.34.1
